newboardconfig.map.qmsg

cyclone II 208c8编写的 图像采集 显示程序。

{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "gpio6 dsp.v(33) " "Info (10035): Verilog HDL or VHDL information at dsp.v(33): object \"gpio6\" declared but not used" {  } { { "dsp.v" "" { Text "F:/newboardconfig9/dsp.v" 33 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "int0 dsp.v(34) " "Info (10035): Verilog HDL or VHDL information at dsp.v(34): object \"int0\" declared but not used" {  } { { "dsp.v" "" { Text "F:/newboardconfig9/dsp.v" 34 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "int1 dsp.v(34) " "Info (10035): Verilog HDL or VHDL information at dsp.v(34): object \"int1\" declared but not used" {  } { { "dsp.v" "" { Text "F:/newboardconfig9/dsp.v" 34 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "int4 dsp.v(34) " "Info (10035): Verilog HDL or VHDL information at dsp.v(34): object \"int4\" declared but not used" {  } { { "dsp.v" "" { Text "F:/newboardconfig9/dsp.v" 34 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "cen3 dsp.v(35) " "Info (10035): Verilog HDL or VHDL information at dsp.v(35): object \"cen3\" declared but not used" {  } { { "dsp.v" "" { Text "F:/newboardconfig9/dsp.v" 35 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "dspdata dsp.v(37) " "Info (10035): Verilog HDL or VHDL information at dsp.v(37): object \"dspdata\" declared but not used" {  } { { "dsp.v" "" { Text "F:/newboardconfig9/dsp.v" 37 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "writefifo1 writefifo1:writefifo11 " "Info: Elaborating entity \"writefifo1\" for hierarchy \"writefifo1:writefifo11\"" {  } { { "newboardconfig.bdf" "writefifo11" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 328 816 1032 520 "writefifo11" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "href_pre writefifo1.v(40) " "Info (10035): Verilog HDL or VHDL information at writefifo1.v(40): object \"href_pre\" declared but not used" {  } { { "writefifo1.v" "" { Text "F:/newboardconfig9/writefifo1.v" 40 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "href_pos writefifo1.v(40) " "Info (10035): Verilog HDL or VHDL information at writefifo1.v(40): object \"href_pos\" declared but not used" {  } { { "writefifo1.v" "" { Text "F:/newboardconfig9/writefifo1.v" 40 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "href_neg writefifo1.v(40) " "Info (10035): Verilog HDL or VHDL information at writefifo1.v(40): object \"href_neg\" declared but not used" {  } { { "writefifo1.v" "" { Text "F:/newboardconfig9/writefifo1.v" 40 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "hsyn_neg writefifo1.v(41) " "Warning (10036): Verilog HDL or VHDL warning at writefifo1.v(41): object \"hsyn_neg\" assigned a value but never read" {  } { { "writefifo1.v" "" { Text "F:/newboardconfig9/writefifo1.v" 41 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "vsyn_neg writefifo1.v(42) " "Warning (10036): Verilog HDL or VHDL warning at writefifo1.v(42): object \"vsyn_neg\" assigned a value but never read" {  } { { "writefifo1.v" "" { Text "F:/newboardconfig9/writefifo1.v" 42 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "fodd_neg writefifo1.v(43) " "Warning (10036): Verilog HDL or VHDL warning at writefifo1.v(43): object \"fodd_neg\" assigned a value but never read" {  } { { "writefifo1.v" "" { Text "F:/newboardconfig9/writefifo1.v" 43 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "fodd_pos_cnt writefifo1.v(44) " "Info (10035): Verilog HDL or VHDL information at writefifo1.v(44): object \"fodd_pos_cnt\" declared but not used" {  } { { "writefifo1.v" "" { Text "F:/newboardconfig9/writefifo1.v" 44 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "fifo1data_reg writefifo1.v(45) " "Info (10035): Verilog HDL or VHDL information at writefifo1.v(45): object \"fifo1data_reg\" declared but not used" {  } { { "writefifo1.v" "" { Text "F:/newboardconfig9/writefifo1.v" 45 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "writefifo1.v(77) " "Info (10264): Verilog HDL Case Statement information at writefifo1.v(77): all case item expressions in this case statement are onehot" {  } { { "writefifo1.v" "" { Text "F:/newboardconfig9/writefifo1.v" 77 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "writefifo1.v(95) " "Info (10264): Verilog HDL Case Statement information at writefifo1.v(95): all case item expressions in this case statement are onehot" {  } { { "writefifo1.v" "" { Text "F:/newboardconfig9/writefifo1.v" 95 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "writefifo1.v(116) " "Info (10264): Verilog HDL Case Statement information at writefifo1.v(116): all case item expressions in this case statement are onehot" {  } { { "writefifo1.v" "" { Text "F:/newboardconfig9/writefifo1.v" 116 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "resetcmos resetcmos:resetcmos1 " "Info: Elaborating entity \"resetcmos\" for hierarchy \"resetcmos:resetcmos1\"" {  } { { "newboardconfig.bdf" "resetcmos1" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { -272 96 264 -176 "resetcmos1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reset_gen resetcmos:resetcmos1\|reset_gen:comsreset1 " "Info: Elaborating entity \"reset_gen\" for hierarchy \"resetcmos:resetcmos1\|reset_gen:comsreset1\"" {  } { { "resetcmos.v" "comsreset1" { Text "F:/newboardconfig9/resetcmos.v" 27 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "altpll0.v 1 1 " "Warning: Using design file altpll0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 altpll0 " "Info: Found entity 1: altpll0" {  } { { "altpll0.v" "" { Text "F:/newboardconfig9/altpll0.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll0 altpll0:inst " "Info: Elaborating entity \"altpll0\" for hierarchy \"altpll0:inst\"" {  } { { "newboardconfig.bdf" "inst" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 720 -208 32 880 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus51/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus51/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/altpll.tdf" 363 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}