newboardconfig.map.qmsg

cyclone II 208c8编写的 图像采集 显示程序。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jan 04 02:10:43 2008 " "Info: Processing started: Fri Jan 04 02:10:43 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off newboardconfig -c newboardconfig " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off newboardconfig -c newboardconfig" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "readfifo1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file readfifo1.v" { { "Info" "ISGN_ENTITY_NAME" "1 readfifo1 " "Info: Found entity 1: readfifo1" {  } { { "readfifo1.v" "" { Text "F:/newboardconfig9/readfifo1.v" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "newboardconfig.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file newboardconfig.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 newboardconfig " "Info: Found entity 1: newboardconfig" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pins.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 pins " "Info: Found entity 1: pins" {  } { { "pins.v" "" { Text "F:/newboardconfig9/pins.v" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "writefifo1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file writefifo1.v" { { "Info" "ISGN_ENTITY_NAME" "1 writefifo1 " "Info: Found entity 1: writefifo1" {  } { { "writefifo1.v" "" { Text "F:/newboardconfig9/writefifo1.v" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dsp.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file dsp.v" { { "Info" "ISGN_ENTITY_NAME" "1 dsp " "Info: Found entity 1: dsp" {  } { { "dsp.v" "" { Text "F:/newboardconfig9/dsp.v" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "reset_gen.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file reset_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 reset_gen " "Info: Found entity 1: reset_gen" {  } { { "reset_gen.v" "" { Text "F:/newboardconfig9/reset_gen.v" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "resetcmos.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file resetcmos.v" { { "Info" "ISGN_ENTITY_NAME" "1 resetcmos " "Info: Found entity 1: resetcmos" {  } { { "resetcmos.v" "" { Text "F:/newboardconfig9/resetcmos.v" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clk_syn.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clk_syn.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_syn " "Info: Found entity 1: clk_syn" {  } { { "clk_syn.v" "" { Text "F:/newboardconfig9/clk_syn.v" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "newboardconfig " "Info: Elaborating entity \"newboardconfig\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "blank " "Warning: Pin \"blank\" is missing source" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 968 -200 -24 984 "blank" "" } } } }  } 0 0 "Pin \"%1!s!\" is missing source" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "vga_clk " "Warning: Pin \"vga_clk\" is missing source" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 1008 -200 -24 1024 "vga_clk" "" } } } }  } 0 0 "Pin \"%1!s!\" is missing source" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "vga_hsyn " "Warning: Pin \"vga_hsyn\" is missing source" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 936 -200 -24 952 "vga_hsyn" "" } } } }  } 0 0 "Pin \"%1!s!\" is missing source" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dsp dsp:dsp1 " "Info: Elaborating entity \"dsp\" for hierarchy \"dsp:dsp1\"" {  } { { "newboardconfig.bdf" "dsp1" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 152 168 360 472 "dsp1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "dspreset dsp.v(31) " "Info (10035): Verilog HDL or VHDL information at dsp.v(31): object \"dspreset\" declared but not used" {  } { { "dsp.v" "" { Text "F:/newboardconfig9/dsp.v" 31 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "dspwe dsp.v(32) " "Info (10035): Verilog HDL or VHDL information at dsp.v(32): object \"dspwe\" declared but not used" {  } { { "dsp.v" "" { Text "F:/newboardconfig9/dsp.v" 32 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "dspoe dsp.v(32) " "Info (10035): Verilog HDL or VHDL information at dsp.v(32): object \"dspoe\" declared but not used" {  } { { "dsp.v" "" { Text "F:/newboardconfig9/dsp.v" 32 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "gpio1 dsp.v(33) " "Info (10035): Verilog HDL or VHDL information at dsp.v(33): object \"gpio1\" declared but not used" {  } { { "dsp.v" "" { Text "F:/newboardconfig9/dsp.v" 33 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "gpio2 dsp.v(33) " "Info (10035): Verilog HDL or VHDL information at dsp.v(33): object \"gpio2\" declared but not used" {  } { { "dsp.v" "" { Text "F:/newboardconfig9/dsp.v" 33 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "gpio3 dsp.v(33) " "Info (10035): Verilog HDL or VHDL information at dsp.v(33): object \"gpio3\" declared but not used" {  } { { "dsp.v" "" { Text "F:/newboardconfig9/dsp.v" 33 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "gpio4 dsp.v(33) " "Info (10035): Verilog HDL or VHDL information at dsp.v(33): object \"gpio4\" declared but not used" {  } { { "dsp.v" "" { Text "F:/newboardconfig9/dsp.v" 33 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}