newboardconfig.hier_info

cyclone II 208c8编写的 图像采集 显示程序。

|newboardconfig
R8019en <= dsp:dsp1.R8019en
dspreset => dsp:dsp1.dspreset
dspre => dsp:dsp1.dspre
dspre => readfifo1:readfifo11.dspre
dspwe => dsp:dsp1.dspwe
dspoe => dsp:dsp1.dspoe
dspoe => readfifo1:readfifo11.dspoe
gpio1 => dsp:dsp1.gpio1
gpio2 => dsp:dsp1.gpio2
gpio3 => dsp:dsp1.gpio3
gpio4 => dsp:dsp1.gpio4
gpio6 => dsp:dsp1.gpio6
int0 => dsp:dsp1.int0
int1 => dsp:dsp1.int1
int4 => dsp:dsp1.int4
cen2 => dsp:dsp1.cen2
cen3 => dsp:dsp1.cen3
dspaddr[0] => dsp:dsp1.dspaddr[0]
dspaddr[1] => dsp:dsp1.dspaddr[1]
dspaddr[2] => dsp:dsp1.dspaddr[2]
dspaddr[3] => dsp:dsp1.dspaddr[3]
dspaddr[4] => dsp:dsp1.dspaddr[4]
dspaddr[5] => dsp:dsp1.dspaddr[5]
dspaddr[6] => dsp:dsp1.dspaddr[6]
dspaddr[7] => dsp:dsp1.dspaddr[7]
dspaddr[8] => dsp:dsp1.dspaddr[8]
dspaddr[9] => dsp:dsp1.dspaddr[9]
dspaddr[10] => dsp:dsp1.dspaddr[10]
dspaddr[11] => dsp:dsp1.dspaddr[11]
dspaddr[12] => dsp:dsp1.dspaddr[12]
dspaddr[13] => dsp:dsp1.dspaddr[13]
dspdata[0] => dsp:dsp1.dspdata[0]
dspdata[1] => dsp:dsp1.dspdata[1]
dspdata[2] => dsp:dsp1.dspdata[2]
dspdata[3] => dsp:dsp1.dspdata[3]
dspdata[4] => dsp:dsp1.dspdata[4]
dspdata[5] => dsp:dsp1.dspdata[5]
dspdata[6] => dsp:dsp1.dspdata[6]
dspdata[7] => dsp:dsp1.dspdata[7]
dspdata[8] => dsp:dsp1.dspdata[8]
dspdata[9] => dsp:dsp1.dspdata[9]
dspdata[10] => dsp:dsp1.dspdata[10]
dspdata[11] => dsp:dsp1.dspdata[11]
dspdata[12] => dsp:dsp1.dspdata[12]
dspdata[13] => dsp:dsp1.dspdata[13]
dspdata[14] => dsp:dsp1.dspdata[14]
dspdata[15] => dsp:dsp1.dspdata[15]
dspready <= dsp:dsp1.dspready
fifo1we <= writefifo1:writefifo11.fifo1we
fpgaclk => altpll0:inst.inclk0
pclk => clk_syn:inst1.pclk
hsyn => clk_syn:inst1.hsyn
vsyn => clk_syn:inst1.href
href => clk_syn:inst1.vsyn
fodd => clk_syn:inst1.fodd
uv[0] <= writefifo1:writefifo11.uv[0]
uv[1] <= writefifo1:writefifo11.uv[1]
uv[2] <= writefifo1:writefifo11.uv[2]
uv[3] <= writefifo1:writefifo11.uv[3]
uv[4] <= writefifo1:writefifo11.uv[4]
uv[5] <= writefifo1:writefifo11.uv[5]
uv[6] <= writefifo1:writefifo11.uv[6]
uv[7] <= writefifo1:writefifo11.uv[7]
y[0] <= writefifo1:writefifo11.y[0]
y[1] <= writefifo1:writefifo11.y[1]
y[2] <= writefifo1:writefifo11.y[2]
y[3] <= writefifo1:writefifo11.y[3]
y[4] <= writefifo1:writefifo11.y[4]
y[5] <= writefifo1:writefifo11.y[5]
y[6] <= writefifo1:writefifo11.y[6]
y[7] <= writefifo1:writefifo11.y[7]
fifo1wrst <= writefifo1:writefifo11.fifo1wrst
cmosreset <= resetcmos:resetcmos1.cmosreset
pwdn <= resetcmos:resetcmos1.pwdn
fifo1re <= readfifo1:readfifo11.fifo1re
fifo1oe <= readfifo1:readfifo11.fifo1oe
fifo1rrst <= readfifo1:readfifo11.fifo1rrst
fifo1rclk <= readfifo1:readfifo11.fifo1rclk
fifo1wclk <= writefifo1:writefifo11.fifo1wclk
blank <= <GND>
vga_clk <= <GND>
vga_hsyn <= <GND>
fifo1data[0] <= writefifo1:writefifo11.fifo1data[0]
fifo1data[1] <= writefifo1:writefifo11.fifo1data[1]
fifo1data[2] <= writefifo1:writefifo11.fifo1data[2]
fifo1data[3] <= writefifo1:writefifo11.fifo1data[3]
fifo1data[4] <= writefifo1:writefifo11.fifo1data[4]
fifo1data[5] <= writefifo1:writefifo11.fifo1data[5]
fifo1data[6] <= writefifo1:writefifo11.fifo1data[6]
fifo1data[7] <= writefifo1:writefifo11.fifo1data[7]
fifo1s[0] <= writefifo1:writefifo11.fifo1s[0]
fifo1s[1] <= writefifo1:writefifo11.fifo1s[1]
fifo1s[2] <= writefifo1:writefifo11.fifo1s[2]
fifo2s[0] <= pins:pins1.fifo2s[0]
fifo2s[1] <= pins:pins1.fifo2s[1]
fifo2s[2] <= pins:pins1.fifo2s[2]
fpgareset => pins:pins1.fpgareset
flashaddr[14] <= pins:pins1.flashaddr[14]
flashaddr[15] <= pins:pins1.flashaddr[15]
flashaddr[16] <= pins:pins1.flashaddr[16]
flashaddr[17] <= pins:pins1.flashaddr[17]
flashaddr[18] <= pins:pins1.flashaddr[18]
flashaddr[19] <= pins:pins1.flashaddr[19]


|newboardconfig|dsp:dsp1
R8019en <= R8019en~0.DB_MAX_OUTPUT_PORT_TYPE
dspready <= <VCC>
cmosrstport <= cmosrstport~5.DB_MAX_OUTPUT_PORT_TYPE
fifo1wrrstport <= fifo1wrrstport~4.DB_MAX_OUTPUT_PORT_TYPE
fifo1rdport <= fifo1rdport~0.DB_MAX_OUTPUT_PORT_TYPE
fifo1rdrstport <= fifo1rdrstport~1.DB_MAX_OUTPUT_PORT_TYPE
dspreset => ~NO_FANOUT~
dspre => cmosrstport~0.IN1
dspwe => ~NO_FANOUT~
dspoe => ~NO_FANOUT~
gpio1 => ~NO_FANOUT~
gpio2 => ~NO_FANOUT~
gpio3 => ~NO_FANOUT~
gpio4 => ~NO_FANOUT~
gpio6 => ~NO_FANOUT~
int0 => ~NO_FANOUT~
int1 => ~NO_FANOUT~
int4 => ~NO_FANOUT~
cen2 => R8019en~0.IN1
cen2 => cmosrstport~0.IN0
cen2 => fifo1wrrstport~0.IN0
cen3 => ~NO_FANOUT~
dspaddr[0] => ~NO_FANOUT~
dspaddr[1] => reduce_and~1.IN4
dspaddr[1] => reduce_and~4.IN1
dspaddr[1] => fifo1wrrstport~3.IN0
dspaddr[1] => fifo1rdrstport~0.IN0
dspaddr[2] => reduce_and~1.IN3
dspaddr[2] => reduce_and~4.IN0
dspaddr[2] => reduce_and~5.IN3
dspaddr[2] => fifo1wrrstport~2.IN0
dspaddr[3] => reduce_and~1.IN2
dspaddr[3] => reduce_and~5.IN2
dspaddr[3] => reduce_and~6.IN2
dspaddr[3] => cmosrstport~3.IN1
dspaddr[4] => reduce_and~1.IN1
dspaddr[4] => reduce_and~3.IN1
dspaddr[4] => reduce_and~5.IN1
dspaddr[4] => reduce_and~6.IN1
dspaddr[5] => reduce_and~1.IN0
dspaddr[5] => reduce_and~3.IN0
dspaddr[5] => reduce_and~5.IN0
dspaddr[5] => reduce_and~6.IN0
dspaddr[6] => reduce_and~0.IN7
dspaddr[6] => cmosrstport~2.IN0
dspaddr[6] => fifo1wrrstport~1.IN0
dspaddr[7] => reduce_and~0.IN6
dspaddr[7] => reduce_and~2.IN6
dspaddr[8] => reduce_and~0.IN5
dspaddr[8] => reduce_and~2.IN5
dspaddr[9] => reduce_and~0.IN4
dspaddr[9] => reduce_and~2.IN4
dspaddr[10] => reduce_and~0.IN3
dspaddr[10] => reduce_and~2.IN3
dspaddr[11] => reduce_and~0.IN2
dspaddr[11] => reduce_and~2.IN2
dspaddr[12] => reduce_and~0.IN1
dspaddr[12] => reduce_and~2.IN1
dspaddr[13] => reduce_and~0.IN0
dspaddr[13] => reduce_and~2.IN0
dspdata[0] => ~NO_FANOUT~
dspdata[1] => ~NO_FANOUT~
dspdata[2] => ~NO_FANOUT~
dspdata[3] => ~NO_FANOUT~
dspdata[4] => ~NO_FANOUT~
dspdata[5] => ~NO_FANOUT~
dspdata[6] => ~NO_FANOUT~
dspdata[7] => ~NO_FANOUT~
dspdata[8] => ~NO_FANOUT~
dspdata[9] => ~NO_FANOUT~
dspdata[10] => ~NO_FANOUT~
dspdata[11] => ~NO_FANOUT~
dspdata[12] => ~NO_FANOUT~
dspdata[13] => ~NO_FANOUT~
dspdata[14] => ~NO_FANOUT~
dspdata[15] => ~NO_FANOUT~


|newboardconfig|writefifo1:writefifo11
fifo1wclk <= fifo1wclkin.DB_MAX_OUTPUT_PORT_TYPE
fifo1we <= fifo1we_reg.DB_MAX_OUTPUT_PORT_TYPE
fifo1wrst <= fifo1wrst_reg.DB_MAX_OUTPUT_PORT_TYPE
fifo1s[0] <= fifo1s~3.DB_MAX_OUTPUT_PORT_TYPE
fifo1s[1] <= fifo1s~2.DB_MAX_OUTPUT_PORT_TYPE
fifo1s[2] <= fifo1s~1.DB_MAX_OUTPUT_PORT_TYPE
fifo1data[0] <= fifo1data[0]~7.DB_MAX_OUTPUT_PORT_TYPE
fifo1data[1] <= fifo1data[1]~6.DB_MAX_OUTPUT_PORT_TYPE
fifo1data[2] <= fifo1data[2]~5.DB_MAX_OUTPUT_PORT_TYPE
fifo1data[3] <= fifo1data[3]~4.DB_MAX_OUTPUT_PORT_TYPE
fifo1data[4] <= fifo1data[4]~3.DB_MAX_OUTPUT_PORT_TYPE
fifo1data[5] <= fifo1data[5]~2.DB_MAX_OUTPUT_PORT_TYPE
fifo1data[6] <= fifo1data[6]~1.DB_MAX_OUTPUT_PORT_TYPE
fifo1data[7] <= fifo1data[7]~0.DB_MAX_OUTPUT_PORT_TYPE
cmosreset => y~0.OE
cmosreset => y~1.OE
cmosreset => y~2.OE
cmosreset => y~3.OE
cmosreset => y~4.OE
cmosreset => y~5.OE
cmosreset => y~6.OE
cmosreset => y~7.OE
cmosreset => uv~8.OE
cmosreset => uv~9.OE
cmosreset => uv~10.OE
cmosreset => uv~11.OE
cmosreset => uv~12.OE
cmosreset => uv~13.OE
cmosreset => uv~14.OE
cmosreset => uv~15.OE
fifo1wclkin => fifo1wclk.DATAIN
pclk => frdata_valid.CLK
pclk => fifo1wrst_reg.CLK
pclk => fifo1we_reg.CLK
pclk => hsyn_pos.CLK
pclk => hsyn_pre.CLK
pclk => vsyn_pos.CLK
pclk => vsyn_pre.CLK
pclk => fodd_pos.CLK
pclk => fodd_pre.CLK
pclk => p_cnt[8].CLK
pclk => p_cnt[7].CLK
pclk => p_cnt[6].CLK
pclk => p_cnt[5].CLK
pclk => p_cnt[4].CLK
pclk => p_cnt[3].CLK
pclk => p_cnt[2].CLK
pclk => p_cnt[1].CLK
pclk => p_cnt[0].CLK
pclk => p_cnt[9].CLK
pclk => h_cnt[8].CLK
pclk => h_cnt[7].CLK
pclk => h_cnt[6].CLK
pclk => h_cnt[5].CLK
pclk => h_cnt[4].CLK
pclk => h_cnt[3].CLK
pclk => h_cnt[2].CLK
pclk => h_cnt[1].CLK
pclk => h_cnt[0].CLK
pclk => h_cnt[9].CLK
pclk => pdata_valid.CLK
pclk => hdata_valid.CLK
pclk => writefifo1_state~5.IN1
hsyn => Decoder~0.IN0
hsyn => hsyn_pre.DATAIN
vsyn => Decoder~1.IN0
vsyn => vsyn_pre.DATAIN
href => p_cnt~0.OUTPUTSELECT
href => p_cnt~1.OUTPUTSELECT
href => p_cnt~2.OUTPUTSELECT
href => p_cnt~3.OUTPUTSELECT
href => p_cnt~4.OUTPUTSELECT
href => p_cnt~5.OUTPUTSELECT
href => p_cnt~6.OUTPUTSELECT
href => p_cnt~7.OUTPUTSELECT
href => p_cnt~8.OUTPUTSELECT
href => p_cnt~9.OUTPUTSELECT
fodd => Decoder~2.IN0
fodd => fodd_pre.DATAIN
y[0] <= y~7
y[1] <= y~6
y[2] <= y~5
y[3] <= y~4
y[4] <= y~3
y[5] <= y~2
y[6] <= y~1
y[7] <= y~0
uv[0] <= uv~15
uv[1] <= uv~14
uv[2] <= uv~13
uv[3] <= uv~12
uv[4] <= uv~11
uv[5] <= uv~10
uv[6] <= uv~9
uv[7] <= uv~8
fifo1wrrstport => frdata_valid.ACLR
fifo1wrrstport => fifo1wrst_reg.ENA
fifo1wrrstport => writefifo1_state~6.IN1
upperframe_readed => Select~0.IN1
upperframe_readed => Select~2.IN3
upperframe_readed => Select~2.IN1
upperframe_readed => Select~1.IN2
upperframe_readed => Select~1.IN3


|newboardconfig|resetcmos:resetcmos1
cmosreset <= reset_gen:comsreset1.rst_out
pwdn <= <GND>
fpgaclk => fpgaclk~0.IN1
cmosrstport => cmosrstport~0.IN1


|newboardconfig|resetcmos:resetcmos1|reset_gen:comsreset1
rst_out <= rst_cnt[17].DB_MAX_OUTPUT_PORT_TYPE
clk => rst_cnt[16].CLK
clk => rst_cnt[15].CLK
clk => rst_cnt[14].CLK
clk => rst_cnt[13].CLK
clk => rst_cnt[12].CLK
clk => rst_cnt[11].CLK
clk => rst_cnt[10].CLK
clk => rst_cnt[9].CLK
clk => rst_cnt[8].CLK
clk => rst_cnt[7].CLK
clk => rst_cnt[6].CLK
clk => rst_cnt[5].CLK
clk => rst_cnt[4].CLK
clk => rst_cnt[3].CLK
clk => rst_cnt[2].CLK
clk => rst_cnt[1].CLK
clk => rst_cnt[0].CLK
clk => rst_cnt[17].CLK
rst_in => rst_cnt[16].ACLR
rst_in => rst_cnt[15].ACLR
rst_in => rst_cnt[14].ACLR
rst_in => rst_cnt[13].ACLR
rst_in => rst_cnt[12].ACLR
rst_in => rst_cnt[11].ACLR
rst_in => rst_cnt[10].ACLR
rst_in => rst_cnt[9].ACLR
rst_in => rst_cnt[8].ACLR
rst_in => rst_cnt[7].ACLR
rst_in => rst_cnt[6].ACLR
rst_in => rst_cnt[5].ACLR
rst_in => rst_cnt[4].ACLR
rst_in => rst_cnt[3].ACLR
rst_in => rst_cnt[2].ACLR
rst_in => rst_cnt[1].ACLR
rst_in => rst_cnt[0].ACLR
rst_in => rst_cnt[17].ACLR


|newboardconfig|altpll0:inst
inclk0 => sub_wire3[0].IN1
c0 <= altpll:altpll_component.clk


|newboardconfig|altpll0:inst|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => pll.CLK1
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
clk[0] <= pll.CLK
clk[1] <= pll.CLK1
clk[2] <= pll.CLK2
clk[3] <= <UNC>
clk[4] <= <UNC>
clk[5] <= <UNC>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= <GND>


|newboardconfig|clk_syn:inst1
pclk_syn <= pclk_syn~reg0.DB_MAX_OUTPUT_PORT_TYPE
pclk_syn1 <= pclk_syn1~reg0.DB_MAX_OUTPUT_PORT_TYPE
hsyn_syn <= hsyn_syn~reg0.DB_MAX_OUTPUT_PORT_TYPE
href_syn <= href_syn~reg0.DB_MAX_OUTPUT_PORT_TYPE
fodd_syn <= fodd_syn~reg0.DB_MAX_OUTPUT_PORT_TYPE
vsyn_syn <= vsyn_syn~reg0.DB_MAX_OUTPUT_PORT_TYPE
pclk => pclk_syn~reg0.DATAIN
pclk => pclk_syn1~reg0.DATAIN
hsyn => hsyn_syn~reg0.DATAIN
href => href_syn~reg0.DATAIN
fodd => fodd_syn~reg0.DATAIN
vsyn => vsyn_syn~reg0.DATAIN
fpgaclkx2 => pclk_syn1~reg0.CLK
fpgaclkx2 => hsyn_syn~reg0.CLK
fpgaclkx2 => href_syn~reg0.CLK
fpgaclkx2 => vsyn_syn~reg0.CLK
fpgaclkx2 => fodd_syn~reg0.CLK
fpgaclkx2 => pclk_syn~reg0.CLK


|newboardconfig|readfifo1:readfifo11
fifo1re <= fifo1re~0.DB_MAX_OUTPUT_PORT_TYPE
fifo1oe <= fifo1oe~0.DB_MAX_OUTPUT_PORT_TYPE
fifo1rrst <= fifo1rdrstport.DB_MAX_OUTPUT_PORT_TYPE
fifo1rclk <= dspre.DB_MAX_OUTPUT_PORT_TYPE
upperframe_readed <= upperframe_readed~reg0.DB_MAX_OUTPUT_PORT_TYPE
dspre => fifo1rclk.DATAIN
dspre => fifo1re_cnt[17].CLK
dspre => fifo1re_cnt[16].CLK
dspre => fifo1re_cnt[15].CLK
dspre => fifo1re_cnt[14].CLK
dspre => fifo1re_cnt[13].CLK
dspre => fifo1re_cnt[12].CLK
dspre => fifo1re_cnt[11].CLK
dspre => fifo1re_cnt[10].CLK
dspre => fifo1re_cnt[9].CLK
dspre => fifo1re_cnt[8].CLK
dspre => fifo1re_cnt[7].CLK
dspre => fifo1re_cnt[6].CLK
dspre => fifo1re_cnt[5].CLK
dspre => fifo1re_cnt[4].CLK
dspre => fifo1re_cnt[3].CLK
dspre => fifo1re_cnt[2].CLK
dspre => fifo1re_cnt[1].CLK
dspre => fifo1re_cnt[0].CLK
dspre => upperframe_readed~reg0.CLK
dspre => fifo1re_cnt[18].CLK
dspoe => fifo1oe~0.IN1
fifo1rdport => fifo1re~0.IN0
fifo1rdport => fifo1oe~0.IN0
fifo1rdport => fifo1re_cnt~19.OUTPUTSELECT
fifo1rdport => fifo1re_cnt~20.OUTPUTSELECT
fifo1rdport => fifo1re_cnt~21.OUTPUTSELECT
fifo1rdport => fifo1re_cnt~22.OUTPUTSELECT
fifo1rdport => fifo1re_cnt~23.OUTPUTSELECT
fifo1rdport => fifo1re_cnt~24.OUTPUTSELECT
fifo1rdport => fifo1re_cnt~25.OUTPUTSELECT
fifo1rdport => fifo1re_cnt~26.OUTPUTSELECT
fifo1rdport => fifo1re_cnt~27.OUTPUTSELECT
fifo1rdport => fifo1re_cnt~28.OUTPUTSELECT
fifo1rdport => fifo1re_cnt~29.OUTPUTSELECT
fifo1rdport => fifo1re_cnt~30.OUTPUTSELECT
fifo1rdport => fifo1re_cnt~31.OUTPUTSELECT
fifo1rdport => fifo1re_cnt~32.OUTPUTSELECT
fifo1rdport => fifo1re_cnt~33.OUTPUTSELECT
fifo1rdport => fifo1re_cnt~34.OUTPUTSELECT
fifo1rdport => fifo1re_cnt~35.OUTPUTSELECT
fifo1rdport => fifo1re_cnt~36.OUTPUTSELECT
fifo1rdport => fifo1re_cnt~37.OUTPUTSELECT
fifo1rdport => upperframe_readed~1.OUTPUTSELECT
fifo1rdrstport => fifo1re~0.IN1
fifo1rdrstport => fifo1rrst.DATAIN
fifo1rdrstport => fifo1re_cnt~38.OUTPUTSELECT
fifo1rdrstport => fifo1re_cnt~39.OUTPUTSELECT
fifo1rdrstport => fifo1re_cnt~40.OUTPUTSELECT
fifo1rdrstport => fifo1re_cnt~41.OUTPUTSELECT
fifo1rdrstport => fifo1re_cnt~42.OUTPUTSELECT
fifo1rdrstport => fifo1re_cnt~43.OUTPUTSELECT
fifo1rdrstport => fifo1re_cnt~44.OUTPUTSELECT
fifo1rdrstport => fifo1re_cnt~45.OUTPUTSELECT
fifo1rdrstport => fifo1re_cnt~46.OUTPUTSELECT
fifo1rdrstport => fifo1re_cnt~47.OUTPUTSELECT
fifo1rdrstport => fifo1re_cnt~48.OUTPUTSELECT
fifo1rdrstport => fifo1re_cnt~49.OUTPUTSELECT
fifo1rdrstport => fifo1re_cnt~50.OUTPUTSELECT
fifo1rdrstport => fifo1re_cnt~51.OUTPUTSELECT
fifo1rdrstport => fifo1re_cnt~52.OUTPUTSELECT
fifo1rdrstport => fifo1re_cnt~53.OUTPUTSELECT
fifo1rdrstport => fifo1re_cnt~54.OUTPUTSELECT
fifo1rdrstport => fifo1re_cnt~55.OUTPUTSELECT
fifo1rdrstport => fifo1re_cnt~56.OUTPUTSELECT
fifo1rdrstport => upperframe_readed~2.OUTPUTSELECT


|newboardconfig|pins:pins1
fifo2s[0] <= fifo2s~3.DB_MAX_OUTPUT_PORT_TYPE
fifo2s[1] <= fifo2s~2.DB_MAX_OUTPUT_PORT_TYPE
fifo2s[2] <= fifo2s~1.DB_MAX_OUTPUT_PORT_TYPE
flashaddr[14] <= <GND>
flashaddr[15] <= <GND>
flashaddr[16] <= <GND>
flashaddr[17] <= <GND>
flashaddr[18] <= <GND>
flashaddr[19] <= <GND>
fpgareset => ~NO_FANOUT~