📄 mux_mib.tdf
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--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_SIZE=8 LPM_WIDTH=5 LPM_WIDTHS=3 data result sel
--VERSION_BEGIN 5.1 cbx_lpm_mux 2005:04:28:09:25:00:SJ cbx_mgl 2005:10:09:07:39:04:SJ VERSION_END
-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--synthesis_resources = lut 25
SUBDESIGN mux_mib
(
data[39..0] : input;
result[4..0] : output;
sel[2..0] : input;
)
VARIABLE
result_node[4..0] : WIRE;
sel_ffs_wire[2..0] : WIRE;
sel_node[2..0] : WIRE;
w_data571w[7..0] : WIRE;
w_data593w[3..0] : WIRE;
w_data594w[3..0] : WIRE;
w_data642w[7..0] : WIRE;
w_data664w[3..0] : WIRE;
w_data665w[3..0] : WIRE;
w_data711w[7..0] : WIRE;
w_data733w[3..0] : WIRE;
w_data734w[3..0] : WIRE;
w_data780w[7..0] : WIRE;
w_data802w[3..0] : WIRE;
w_data803w[3..0] : WIRE;
w_data849w[7..0] : WIRE;
w_data871w[3..0] : WIRE;
w_data872w[3..0] : WIRE;
w_result591w : WIRE;
w_result592w : WIRE;
w_result599w : WIRE;
w_result620w : WIRE;
w_result662w : WIRE;
w_result663w : WIRE;
w_result670w : WIRE;
w_result691w : WIRE;
w_result731w : WIRE;
w_result732w : WIRE;
w_result739w : WIRE;
w_result760w : WIRE;
w_result800w : WIRE;
w_result801w : WIRE;
w_result808w : WIRE;
w_result829w : WIRE;
w_result869w : WIRE;
w_result870w : WIRE;
w_result877w : WIRE;
w_result898w : WIRE;
w_sel595w[1..0] : WIRE;
w_sel666w[1..0] : WIRE;
w_sel735w[1..0] : WIRE;
w_sel804w[1..0] : WIRE;
w_sel873w[1..0] : WIRE;
BEGIN
result[] = result_node[];
result_node[] = ( ((sel_node[2..2] & w_result870w) # ((! sel_node[2..2]) & w_result869w)), ((sel_node[2..2] & w_result801w) # ((! sel_node[2..2]) & w_result800w)), ((sel_node[2..2] & w_result732w) # ((! sel_node[2..2]) & w_result731w)), ((sel_node[2..2] & w_result663w) # ((! sel_node[2..2]) & w_result662w)), ((sel_node[2..2] & w_result592w) # ((! sel_node[2..2]) & w_result591w)));
sel_ffs_wire[] = ( sel[2..0]);
sel_node[] = ( sel_ffs_wire[2..2], sel[1..0]);
w_data571w[] = ( data[35..35], data[30..30], data[25..25], data[20..20], data[15..15], data[10..10], data[5..5], data[0..0]);
w_data593w[3..0] = w_data571w[3..0];
w_data594w[3..0] = w_data571w[7..4];
w_data642w[] = ( data[36..36], data[31..31], data[26..26], data[21..21], data[16..16], data[11..11], data[6..6], data[1..1]);
w_data664w[3..0] = w_data642w[3..0];
w_data665w[3..0] = w_data642w[7..4];
w_data711w[] = ( data[37..37], data[32..32], data[27..27], data[22..22], data[17..17], data[12..12], data[7..7], data[2..2]);
w_data733w[3..0] = w_data711w[3..0];
w_data734w[3..0] = w_data711w[7..4];
w_data780w[] = ( data[38..38], data[33..33], data[28..28], data[23..23], data[18..18], data[13..13], data[8..8], data[3..3]);
w_data802w[3..0] = w_data780w[3..0];
w_data803w[3..0] = w_data780w[7..4];
w_data849w[] = ( data[39..39], data[34..34], data[29..29], data[24..24], data[19..19], data[14..14], data[9..9], data[4..4]);
w_data871w[3..0] = w_data849w[3..0];
w_data872w[3..0] = w_data849w[7..4];
w_result591w = (((w_data593w[1..1] & w_sel595w[0..0]) & (! w_result599w)) # (w_result599w & (w_data593w[3..3] # (! w_sel595w[0..0]))));
w_result592w = (((w_data594w[1..1] & w_sel595w[0..0]) & (! w_result620w)) # (w_result620w & (w_data594w[3..3] # (! w_sel595w[0..0]))));
w_result599w = (((w_data593w[0..0] & (! w_sel595w[1..1])) & (! w_sel595w[0..0])) # (w_sel595w[1..1] & (w_sel595w[0..0] # w_data593w[2..2])));
w_result620w = (((w_data594w[0..0] & (! w_sel595w[1..1])) & (! w_sel595w[0..0])) # (w_sel595w[1..1] & (w_sel595w[0..0] # w_data594w[2..2])));
w_result662w = (((w_data664w[1..1] & w_sel666w[0..0]) & (! w_result670w)) # (w_result670w & (w_data664w[3..3] # (! w_sel666w[0..0]))));
w_result663w = (((w_data665w[1..1] & w_sel666w[0..0]) & (! w_result691w)) # (w_result691w & (w_data665w[3..3] # (! w_sel666w[0..0]))));
w_result670w = (((w_data664w[0..0] & (! w_sel666w[1..1])) & (! w_sel666w[0..0])) # (w_sel666w[1..1] & (w_sel666w[0..0] # w_data664w[2..2])));
w_result691w = (((w_data665w[0..0] & (! w_sel666w[1..1])) & (! w_sel666w[0..0])) # (w_sel666w[1..1] & (w_sel666w[0..0] # w_data665w[2..2])));
w_result731w = (((w_data733w[1..1] & w_sel735w[0..0]) & (! w_result739w)) # (w_result739w & (w_data733w[3..3] # (! w_sel735w[0..0]))));
w_result732w = (((w_data734w[1..1] & w_sel735w[0..0]) & (! w_result760w)) # (w_result760w & (w_data734w[3..3] # (! w_sel735w[0..0]))));
w_result739w = (((w_data733w[0..0] & (! w_sel735w[1..1])) & (! w_sel735w[0..0])) # (w_sel735w[1..1] & (w_sel735w[0..0] # w_data733w[2..2])));
w_result760w = (((w_data734w[0..0] & (! w_sel735w[1..1])) & (! w_sel735w[0..0])) # (w_sel735w[1..1] & (w_sel735w[0..0] # w_data734w[2..2])));
w_result800w = (((w_data802w[1..1] & w_sel804w[0..0]) & (! w_result808w)) # (w_result808w & (w_data802w[3..3] # (! w_sel804w[0..0]))));
w_result801w = (((w_data803w[1..1] & w_sel804w[0..0]) & (! w_result829w)) # (w_result829w & (w_data803w[3..3] # (! w_sel804w[0..0]))));
w_result808w = (((w_data802w[0..0] & (! w_sel804w[1..1])) & (! w_sel804w[0..0])) # (w_sel804w[1..1] & (w_sel804w[0..0] # w_data802w[2..2])));
w_result829w = (((w_data803w[0..0] & (! w_sel804w[1..1])) & (! w_sel804w[0..0])) # (w_sel804w[1..1] & (w_sel804w[0..0] # w_data803w[2..2])));
w_result869w = (((w_data871w[1..1] & w_sel873w[0..0]) & (! w_result877w)) # (w_result877w & (w_data871w[3..3] # (! w_sel873w[0..0]))));
w_result870w = (((w_data872w[1..1] & w_sel873w[0..0]) & (! w_result898w)) # (w_result898w & (w_data872w[3..3] # (! w_sel873w[0..0]))));
w_result877w = (((w_data871w[0..0] & (! w_sel873w[1..1])) & (! w_sel873w[0..0])) # (w_sel873w[1..1] & (w_sel873w[0..0] # w_data871w[2..2])));
w_result898w = (((w_data872w[0..0] & (! w_sel873w[1..1])) & (! w_sel873w[0..0])) # (w_sel873w[1..1] & (w_sel873w[0..0] # w_data872w[2..2])));
w_sel595w[1..0] = sel_node[1..0];
w_sel666w[1..0] = sel_node[1..0];
w_sel735w[1..0] = sel_node[1..0];
w_sel804w[1..0] = sel_node[1..0];
w_sel873w[1..0] = sel_node[1..0];
END;
--VALID FILE
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