altsyncram_ofb1.tdf

cyclone II 208c8编写的 图像采集 显示程序。

			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 20480,
			PORT_A_FIRST_BIT_NUMBER = 2,
			PORT_A_LAST_ADDRESS = 24575,
			PORT_A_LOGICAL_RAM_DEPTH = 32768,
			PORT_A_LOGICAL_RAM_WIDTH = 3,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 20480,
			PORT_B_FIRST_BIT_NUMBER = 2,
			PORT_B_LAST_ADDRESS = 24575,
			PORT_B_LOGICAL_RAM_DEPTH = 32768,
			PORT_B_LOGICAL_RAM_WIDTH = 3,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block2a18 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 28671,
			PORT_A_LOGICAL_RAM_DEPTH = 32768,
			PORT_A_LOGICAL_RAM_WIDTH = 3,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 24576,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 28671,
			PORT_B_LOGICAL_RAM_DEPTH = 32768,
			PORT_B_LOGICAL_RAM_WIDTH = 3,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block2a19 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 1,
			PORT_A_LAST_ADDRESS = 28671,
			PORT_A_LOGICAL_RAM_DEPTH = 32768,
			PORT_A_LOGICAL_RAM_WIDTH = 3,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 24576,
			PORT_B_FIRST_BIT_NUMBER = 1,
			PORT_B_LAST_ADDRESS = 28671,
			PORT_B_LOGICAL_RAM_DEPTH = 32768,
			PORT_B_LOGICAL_RAM_WIDTH = 3,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block2a20 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 2,
			PORT_A_LAST_ADDRESS = 28671,
			PORT_A_LOGICAL_RAM_DEPTH = 32768,
			PORT_A_LOGICAL_RAM_WIDTH = 3,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 24576,
			PORT_B_FIRST_BIT_NUMBER = 2,
			PORT_B_LAST_ADDRESS = 28671,
			PORT_B_LOGICAL_RAM_DEPTH = 32768,
			PORT_B_LOGICAL_RAM_WIDTH = 3,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block2a21 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 28672,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 32768,
			PORT_A_LOGICAL_RAM_WIDTH = 3,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 28672,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 32767,
			PORT_B_LOGICAL_RAM_DEPTH = 32768,
			PORT_B_LOGICAL_RAM_WIDTH = 3,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block2a22 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 28672,
			PORT_A_FIRST_BIT_NUMBER = 1,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 32768,
			PORT_A_LOGICAL_RAM_WIDTH = 3,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 28672,
			PORT_B_FIRST_BIT_NUMBER = 1,
			PORT_B_LAST_ADDRESS = 32767,
			PORT_B_LOGICAL_RAM_DEPTH = 32768,
			PORT_B_LOGICAL_RAM_WIDTH = 3,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block2a23 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 28672,
			PORT_A_FIRST_BIT_NUMBER = 2,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 32768,
			PORT_A_LOGICAL_RAM_WIDTH = 3,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 28672,
			PORT_B_FIRST_BIT_NUMBER = 2,
			PORT_B_LAST_ADDRESS = 32767,
			PORT_B_LOGICAL_RAM_DEPTH = 32768,
			PORT_B_LOGICAL_RAM_WIDTH = 3,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	address_a_wire[14..0]	: WIRE;
	address_b_wire[14..0]	: WIRE;
	clocken1	: NODE;

BEGIN 
	address_reg_a[].CLK = clock0;
	address_reg_a[].D = address_a[14..12];
	address_reg_a[].ENA = clocken0;
	address_reg_b[].CLK = clock1;
	address_reg_b[].D = address_b[14..12];
	address_reg_b[].ENA = clocken1;
	decode3.data[2..0] = address_a_wire[14..12];
	decode3.enable = wren_a;
	decode4.data[2..0] = address_b_wire[14..12];
	decode4.enable = wren_b;
	decode_a.data[2..0] = address_a_wire[14..12];
	decode_a.enable = clocken0;
	decode_b.data[2..0] = address_b_wire[14..12];
	decode_b.enable = B"1";
	mux5.data[] = ( ram_block2a[23..0].portadataout[0..0]);
	mux5.sel[] = address_reg_a[].Q;
	mux6.data[] = ( ram_block2a[23..0].portbdataout[0..0]);
	mux6.sel[] = address_reg_b[].Q;
	ram_block2a[23..0].clk0 = clock0;
	ram_block2a[23..0].clk1 = clock1;
	ram_block2a[23..0].ena0 = ( decode_a.eq[7..7], decode_a.eq[7..7], decode_a.eq[7..6], decode_a.eq[6..6], decode_a.eq[6..5], decode_a.eq[5..5], decode_a.eq[5..4], decode_a.eq[4..4], decode_a.eq[4..3], decode_a.eq[3..3], decode_a.eq[3..2], decode_a.eq[2..2], decode_a.eq[2..1], decode_a.eq[1..1], decode_a.eq[1..0], decode_a.eq[0..0], decode_a.eq[0..0]);
	ram_block2a[23..0].ena1 = ( decode_b.eq[7..7], decode_b.eq[7..7], decode_b.eq[7..6], decode_b.eq[6..6], decode_b.eq[6..5], decode_b.eq[5..5], decode_b.eq[5..4], decode_b.eq[4..4], decode_b.eq[4..3], decode_b.eq[3..3], decode_b.eq[3..2], decode_b.eq[2..2], decode_b.eq[2..1], decode_b.eq[1..1], decode_b.eq[1..0], decode_b.eq[0..0], decode_b.eq[0..0]);
	ram_block2a[23..0].portaaddr[] = ( address_a_wire[11..0]);
	ram_block2a[0].portadatain[] = ( data_a[0..0]);
	ram_block2a[1].portadatain[] = ( data_a[1..1]);
	ram_block2a[2].portadatain[] = ( data_a[2..2]);
	ram_block2a[3].portadatain[] = ( data_a[0..0]);
	ram_block2a[4].portadatain[] = ( data_a[1..1]);
	ram_block2a[5].portadatain[] = ( data_a[2..2]);
	ram_block2a[6].portadatain[] = ( data_a[0..0]);
	ram_block2a[7].portadatain[] = ( data_a[1..1]);
	ram_block2a[8].portadatain[] = ( data_a[2..2]);
	ram_block2a[9].portadatain[] = ( data_a[0..0]);
	ram_block2a[10].portadatain[] = ( data_a[1..1]);
	ram_block2a[11].portadatain[] = ( data_a[2..2]);
	ram_block2a[12].portadatain[] = ( data_a[0..0]);
	ram_block2a[13].portadatain[] = ( data_a[1..1]);
	ram_block2a[14].portadatain[] = ( data_a[2..2]);
	ram_block2a[15].portadatain[] = ( data_a[0..0]);
	ram_block2a[16].portadatain[] = ( data_a[1..1]);
	ram_block2a[17].portadatain[] = ( data_a[2..2]);
	ram_block2a[18].portadatain[] = ( data_a[0..0]);
	ram_block2a[19].portadatain[] = ( data_a[1..1]);
	ram_block2a[20].portadatain[] = ( data_a[2..2]);
	ram_block2a[21].portadatain[] = ( data_a[0..0]);
	ram_block2a[22].portadatain[] = ( data_a[1..1]);
	ram_block2a[23].portadatain[] = ( data_a[2..2]);
	ram_block2a[23..0].portawe = ( decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..6], decode3.eq[6..6], decode3.eq[6..5], decode3.eq[5..5], decode3.eq[5..4], decode3.eq[4..4], decode3.eq[4..3], decode3.eq[3..3], decode3.eq[3..2], decode3.eq[2..2], decode3.eq[2..1], decode3.eq[1..1], decode3.eq[1..0], decode3.eq[0..0], decode3.eq[0..0]);
	ram_block2a[23..0].portbaddr[] = ( address_b_wire[11..0]);
	ram_block2a[0].portbdatain[] = ( data_b[0..0]);
	ram_block2a[1].portbdatain[] = ( data_b[1..1]);
	ram_block2a[2].portbdatain[] = ( data_b[2..2]);
	ram_block2a[3].portbdatain[] = ( data_b[0..0]);
	ram_block2a[4].portbdatain[] = ( data_b[1..1]);
	ram_block2a[5].portbdatain[] = ( data_b[2..2]);
	ram_block2a[6].portbdatain[] = ( data_b[0..0]);
	ram_block2a[7].portbdatain[] = ( data_b[1..1]);
	ram_block2a[8].portbdatain[] = ( data_b[2..2]);
	ram_block2a[9].portbdatain[] = ( data_b[0..0]);
	ram_block2a[10].portbdatain[] = ( data_b[1..1]);
	ram_block2a[11].portbdatain[] = ( data_b[2..2]);
	ram_block2a[12].portbdatain[] = ( data_b[0..0]);
	ram_block2a[13].portbdatain[] = ( data_b[1..1]);
	ram_block2a[14].portbdatain[] = ( data_b[2..2]);
	ram_block2a[15].portbdatain[] = ( data_b[0..0]);
	ram_block2a[16].portbdatain[] = ( data_b[1..1]);
	ram_block2a[17].portbdatain[] = ( data_b[2..2]);
	ram_block2a[18].portbdatain[] = ( data_b[0..0]);
	ram_block2a[19].portbdatain[] = ( data_b[1..1]);
	ram_block2a[20].portbdatain[] = ( data_b[2..2]);
	ram_block2a[21].portbdatain[] = ( data_b[0..0]);
	ram_block2a[22].portbdatain[] = ( data_b[1..1]);
	ram_block2a[23].portbdatain[] = ( data_b[2..2]);
	ram_block2a[23..0].portbrewe = ( decode4.eq[7..7], decode4.eq[7..7], decode4.eq[7..6], decode4.eq[6..6], decode4.eq[6..5], decode4.eq[5..5], decode4.eq[5..4], decode4.eq[4..4], decode4.eq[4..3], decode4.eq[3..3], decode4.eq[3..2], decode4.eq[2..2], decode4.eq[2..1], decode4.eq[1..1], decode4.eq[1..0], decode4.eq[0..0], decode4.eq[0..0]);
	address_a_wire[] = address_a[];
	address_b_wire[] = address_b[];
	clocken1 = VCC;
	q_a[] = mux5.result[];
	q_b[] = mux6.result[];
END;
--VALID FILE