newboardconfig.tan.qmsg

cyclone II 208c8编写的 图像采集 显示程序。

{ "Info" "ITDB_FULL_SLACK_RESULT" "dspre register readfifo1:readfifo11\|fifo1re_cnt\[7\] register readfifo1:readfifo11\|fifo1re_cnt\[7\] 9.204 ns " "Info: Slack time is 9.204 ns for clock \"dspre\" between source register \"readfifo1:readfifo11\|fifo1re_cnt\[7\]\" and destination register \"readfifo1:readfifo11\|fifo1re_cnt\[7\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "134.01 MHz 7.462 ns " "Info: Fmax is 134.01 MHz (period= 7.462 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "16.402 ns + Largest register register " "Info: + Largest register to register requirement is 16.402 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "16.666 ns + " "Info: + Setup relationship between source and destination is 16.666 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 24.999 ns " "Info: + Latch edge is 24.999 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination dspre 16.666 ns 8.333 ns inverted 50 " "Info: Clock period of Destination clock \"dspre\" is 16.666 ns with inverted offset of 8.333 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 8.333 ns " "Info: - Launch edge is 8.333 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source dspre 16.666 ns 8.333 ns inverted 50 " "Info: Clock period of Source clock \"dspre\" is 16.666 ns with inverted offset of 8.333 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "dspre destination 7.883 ns + Shortest register " "Info: + Shortest clock path from clock \"dspre\" to destination register is 7.883 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.005 ns) 1.005 ns dspre 1 CLK PIN_3 22 " "Info: 1: + IC(0.000 ns) + CELL(1.005 ns) = 1.005 ns; Loc. = PIN_3; Fanout = 22; CLK Node = 'dspre'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { dspre } "NODE_NAME" } "" } } { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 176 -400 -232 192 "dspre" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.212 ns) + CELL(0.666 ns) 7.883 ns readfifo1:readfifo11\|fifo1re_cnt\[7\] 2 REG LCFF_X19_Y18_N29 3 " "Info: 2: + IC(6.212 ns) + CELL(0.666 ns) = 7.883 ns; Loc. = LCFF_X19_Y18_N29; Fanout = 3; REG Node = 'readfifo1:readfifo11\|fifo1re_cnt\[7\]'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "6.878 ns" { dspre readfifo1:readfifo11|fifo1re_cnt[7] } "NODE_NAME" } "" } } { "readfifo1.v" "" { Text "F:/newboardconfig9/readfifo1.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.671 ns ( 21.20 % ) " "Info: Total cell delay = 1.671 ns ( 21.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.212 ns ( 78.80 % ) " "Info: Total interconnect delay = 6.212 ns ( 78.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "7.883 ns" { dspre readfifo1:readfifo11|fifo1re_cnt[7] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "7.883 ns" { dspre dspre~combout readfifo1:readfifo11|fifo1re_cnt[7] } { 0.000ns 0.000ns 6.212ns } { 0.000ns 1.005ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "dspre source 7.883 ns - Longest register " "Info: - Longest clock path from clock \"dspre\" to source register is 7.883 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.005 ns) 1.005 ns dspre 1 CLK PIN_3 22 " "Info: 1: + IC(0.000 ns) + CELL(1.005 ns) = 1.005 ns; Loc. = PIN_3; Fanout = 22; CLK Node = 'dspre'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { dspre } "NODE_NAME" } "" } } { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 176 -400 -232 192 "dspre" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.212 ns) + CELL(0.666 ns) 7.883 ns readfifo1:readfifo11\|fifo1re_cnt\[7\] 2 REG LCFF_X19_Y18_N29 3 " "Info: 2: + IC(6.212 ns) + CELL(0.666 ns) = 7.883 ns; Loc. = LCFF_X19_Y18_N29; Fanout = 3; REG Node = 'readfifo1:readfifo11\|fifo1re_cnt\[7\]'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "6.878 ns" { dspre readfifo1:readfifo11|fifo1re_cnt[7] } "NODE_NAME" } "" } } { "readfifo1.v" "" { Text "F:/newboardconfig9/readfifo1.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.671 ns ( 21.20 % ) " "Info: Total cell delay = 1.671 ns ( 21.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.212 ns ( 78.80 % ) " "Info: Total interconnect delay = 6.212 ns ( 78.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "7.883 ns" { dspre readfifo1:readfifo11|fifo1re_cnt[7] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "7.883 ns" { dspre dspre~combout readfifo1:readfifo11|fifo1re_cnt[7] } { 0.000ns 0.000ns 6.212ns } { 0.000ns 1.005ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "7.883 ns" { dspre readfifo1:readfifo11|fifo1re_cnt[7] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "7.883 ns" { dspre dspre~combout readfifo1:readfifo11|fifo1re_cnt[7] } { 0.000ns 0.000ns 6.212ns } { 0.000ns 1.005ns 0.666ns } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "7.883 ns" { dspre readfifo1:readfifo11|fifo1re_cnt[7] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "7.883 ns" { dspre dspre~combout readfifo1:readfifo11|fifo1re_cnt[7] } { 0.000ns 0.000ns 6.212ns } { 0.000ns 1.005ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "readfifo1.v" "" { Text "F:/newboardconfig9/readfifo1.v" 68 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns - " "Info: - Micro setup delay of destination is -0.040 ns" {  } { { "readfifo1.v" "" { Text "F:/newboardconfig9/readfifo1.v" 68 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "7.883 ns" { dspre readfifo1:readfifo11|fifo1re_cnt[7] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "7.883 ns" { dspre dspre~combout readfifo1:readfifo11|fifo1re_cnt[7] } { 0.000ns 0.000ns 6.212ns } { 0.000ns 1.005ns 0.666ns } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "7.883 ns" { dspre readfifo1:readfifo11|fifo1re_cnt[7] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "7.883 ns" { dspre dspre~combout readfifo1:readfifo11|fifo1re_cnt[7] } { 0.000ns 0.000ns 6.212ns } { 0.000ns 1.005ns 0.666ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.198 ns - Longest register register " "Info: - Longest register to register delay is 7.198 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns readfifo1:readfifo11\|fifo1re_cnt\[7\] 1 REG LCFF_X19_Y18_N29 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y18_N29; Fanout = 3; REG Node = 'readfifo1:readfifo11\|fifo1re_cnt\[7\]'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { readfifo1:readfifo11|fifo1re_cnt[7] } "NODE_NAME" } "" } } { "readfifo1.v" "" { Text "F:/newboardconfig9/readfifo1.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.792 ns) + CELL(0.651 ns) 1.443 ns rtl~137 2 COMB LCCOMB_X19_Y18_N8 1 " "Info: 2: + IC(0.792 ns) + CELL(0.651 ns) = 1.443 ns; Loc. = LCCOMB_X19_Y18_N8; Fanout = 1; COMB Node = 'rtl~137'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "1.443 ns" { readfifo1:readfifo11|fifo1re_cnt[7] rtl~137 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.451 ns) + CELL(0.651 ns) 3.545 ns rtl~140 3 COMB LCCOMB_X19_Y17_N28 1 " "Info: 3: + IC(1.451 ns) + CELL(0.651 ns) = 3.545 ns; Loc. = LCCOMB_X19_Y17_N28; Fanout = 1; COMB Node = 'rtl~140'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "2.102 ns" { rtl~137 rtl~140 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.370 ns) + CELL(0.624 ns) 4.539 ns rtl~0 4 COMB LCCOMB_X19_Y17_N26 2 " "Info: 4: + IC(0.370 ns) + CELL(0.624 ns) = 4.539 ns; Loc. = LCCOMB_X19_Y17_N26; Fanout = 2; COMB Node = 'rtl~0'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "0.994 ns" { rtl~140 rtl~0 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.379 ns) + CELL(0.624 ns) 5.542 ns readfifo1:readfifo11\|fifo1re_cnt\[18\]~441 5 COMB LCCOMB_X19_Y17_N24 19 " "Info: 5: + IC(0.379 ns) + CELL(0.624 ns) = 5.542 ns; Loc. = LCCOMB_X19_Y17_N24; Fanout = 19; COMB Node = 'readfifo1:readfifo11\|fifo1re_cnt\[18\]~441'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "1.003 ns" { rtl~0 readfifo1:readfifo11|fifo1re_cnt[18]~441 } "NODE_NAME" } "" } } { "readfifo1.v" "" { Text "F:/newboardconfig9/readfifo1.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.996 ns) + CELL(0.660 ns) 7.198 ns readfifo1:readfifo11\|fifo1re_cnt\[7\] 6 REG LCFF_X19_Y18_N29 3 " "Info: 6: + IC(0.996 ns) + CELL(0.660 ns) = 7.198 ns; Loc. = LCFF_X19_Y18_N29; Fanout = 3; REG Node = 'readfifo1:readfifo11\|fifo1re_cnt\[7\]'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "1.656 ns" { readfifo1:readfifo11|fifo1re_cnt[18]~441 readfifo1:readfifo11|fifo1re_cnt[7] } "NODE_NAME" } "" } } { "readfifo1.v" "" { Text "F:/newboardconfig9/readfifo1.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.210 ns ( 44.60 % ) " "Info: Total cell delay = 3.210 ns ( 44.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.988 ns ( 55.40 % ) " "Info: Total interconnect delay = 3.988 ns ( 55.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "7.198 ns" { readfifo1:readfifo11|fifo1re_cnt[7] rtl~137 rtl~140 rtl~0 readfifo1:readfifo11|fifo1re_cnt[18]~441 readfifo1:readfifo11|fifo1re_cnt[7] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "7.198 ns" { readfifo1:readfifo11|fifo1re_cnt[7] rtl~137 rtl~140 rtl~0 readfifo1:readfifo11|fifo1re_cnt[18]~441 readfifo1:readfifo11|fifo1re_cnt[7] } { 0.000ns 0.792ns 1.451ns 0.370ns 0.379ns 0.996ns } { 0.000ns 0.651ns 0.651ns 0.624ns 0.624ns 0.660ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "7.883 ns" { dspre readfifo1:readfifo11|fifo1re_cnt[7] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "7.883 ns" { dspre dspre~combout readfifo1:readfifo11|fifo1re_cnt[7] } { 0.000ns 0.000ns 6.212ns } { 0.000ns 1.005ns 0.666ns } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "7.883 ns" { dspre readfifo1:readfifo11|fifo1re_cnt[7] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "7.883 ns" { dspre dspre~combout readfifo1:readfifo11|fifo1re_cnt[7] } { 0.000ns 0.000ns 6.212ns } { 0.000ns 1.005ns 0.666ns } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "7.198 ns" { readfifo1:readfifo11|fifo1re_cnt[7] rtl~137 rtl~140 rtl~0 readfifo1:readfifo11|fifo1re_cnt[18]~441 readfifo1:readfifo11|fifo1re_cnt[7] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "7.198 ns" { readfifo1:readfifo11|fifo1re_cnt[7] rtl~137 rtl~140 rtl~0 readfifo1:readfifo11|fifo1re_cnt[18]~441 readfifo1:readfifo11|fifo1re_cnt[7] } { 0.000ns 0.792ns 1.451ns 0.370ns 0.379ns 0.996ns } { 0.000ns 0.651ns 0.651ns 0.624ns 0.624ns 0.660ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "altpll0:inst\|altpll:altpll_component\|_clk0 register writefifo1:writefifo11\|writefifo1_state.WRITE_UPPART register writefifo1:writefifo11\|writefifo1_state.WRITE_UPPART 499 ps " "Info: Minimum slack time is 499 ps for clock \"altpll0:inst\|altpll:altpll_component\|_clk0\" between source register \"writefifo1:writefifo11\|writefifo1_state.WRITE_UPPART\" and destination register \"writefifo1:writefifo11\|writefifo1_state.WRITE_UPPART\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.501 ns + Shortest register register " "Info: + Shortest register to register delay is 0.501 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns writefifo1:writefifo11\|writefifo1_state.WRITE_UPPART 1 REG LCFF_X19_Y15_N17 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y15_N17; Fanout = 3; REG Node = 'writefifo1:writefifo11\|writefifo1_state.WRITE_UPPART'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { writefifo1:writefifo11|writefifo1_state.WRITE_UPPART } "NODE_NAME" } "" } } { "writefifo1.v" "" { Text "F:/newboardconfig9/writefifo1.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.393 ns) 0.393 ns writefifo1:writefifo11\|Select~77 2 COMB LCCOMB_X19_Y15_N16 1 " "Info: 2: + IC(0.000 ns) + CELL(0.393 ns) = 0.393 ns; Loc. = LCCOMB_X19_Y15_N16; Fanout = 1; COMB Node = 'writefifo1:writefifo11\|Select~77'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "0.393 ns" { writefifo1:writefifo11|writefifo1_state.WRITE_UPPART writefifo1:writefifo11|Select~77 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 0.501 ns writefifo1:writefifo11\|writefifo1_state.WRITE_UPPART 3 REG LCFF_X19_Y15_N17 3 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.501 ns; Loc. = LCFF_X19_Y15_N17; Fanout = 3; REG Node = 'writefifo1:writefifo11\|writefifo1_state.WRITE_UPPART'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "0.108 ns" { writefifo1:writefifo11|Select~77 writefifo1:writefifo11|writefifo1_state.WRITE_UPPART } "NODE_NAME" } "" } } { "writefifo1.v" "" { Text "F:/newboardconfig9/writefifo1.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.501 ns ( 100.00 % ) " "Info: Total cell delay = 0.501 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "0.501 ns" { writefifo1:writefifo11|writefifo1_state.WRITE_UPPART writefifo1:writefifo11|Select~77 writefifo1:writefifo11|writefifo1_state.WRITE_UPPART } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "0.501 ns" { writefifo1:writefifo11|writefifo1_state.WRITE_UPPART writefifo1:writefifo11|Select~77 writefifo1:writefifo11|writefifo1_state.WRITE_UPPART } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.002 ns - Smallest register register " "Info: - Smallest register to register requirement is 0.002 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 6.043 ns " "Info: + Latch edge is 6.043 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination altpll0:inst\|altpll:altpll_component\|_clk0 16.666 ns 6.043 ns inverted 50 " "Info: Clock period of Destination clock \"altpll0:inst\|altpll:altpll_component\|_clk0\" is 16.666 ns with inverted offset of 6.043 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 6.043 ns " "Info: - Launch edge is 6.043 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source altpll0:inst\|altpll:altpll_component\|_clk0 16.666 ns 6.043 ns inverted 50 " "Info: Clock period of Source clock \"altpll0:inst\|altpll:altpll_component\|_clk0\" is 16.666 ns with inverted offset of 6.043 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst\|altpll:altpll_component\|_clk0 destination 6.451 ns + Longest register " "Info: + Longest clock path from clock \"altpll0:inst\|altpll:altpll_component\|_clk0\" to destination register is 6.451 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll0:inst\|altpll:altpll_component\|_clk0'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { altpll0:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.211 ns) + CELL(0.000 ns) 1.211 ns altpll0:inst\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 23 " "Info: 2: + IC(1.211 ns) + CELL(0.000 ns) = 1.211 ns; Loc. = CLKCTRL_G3; Fanout = 23; COMB Node = 'altpll0:inst\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "1.211 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.876 ns) + CELL(0.970 ns) 3.057 ns clk_syn:inst1\|pclk_syn1 3 REG LCFF_X16_Y10_N9 2 " "Info: 3: + IC(0.876 ns) + CELL(0.970 ns) = 3.057 ns; Loc. = LCFF_X16_Y10_N9; Fanout = 2; REG Node = 'clk_syn:inst1\|pclk_syn1'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "1.846 ns" { altpll0:inst|altpll:altpll_component|_clk0~clkctrl clk_syn:inst1|pclk_syn1 } "NODE_NAME" } "" } } { "clk_syn.v" "" { Text "F:/newboardconfig9/clk_syn.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.825 ns) + CELL(0.000 ns) 4.882 ns clk_syn:inst1\|pclk_syn1~clkctrl 4 COMB CLKCTRL_G7 35 " "Info: 4: + IC(1.825 ns) + CELL(0.000 ns) = 4.882 ns; Loc. = CLKCTRL_G7; Fanout = 35; COMB Node = 'clk_syn:inst1\|pclk_syn1~clkctrl'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "1.825 ns" { clk_syn:inst1|pclk_syn1 clk_syn:inst1|pclk_syn1~clkctrl } "NODE_NAME" } "" } } { "clk_syn.v" "" { Text "F:/newboardconfig9/clk_syn.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.903 ns) + CELL(0.666 ns) 6.451 ns writefifo1:writefifo11\|writefifo1_state.WRITE_UPPART 5 REG LCFF_X19_Y15_N17 3 " "Info: 5: + IC(0.903 ns) + CELL(0.666 ns) = 6.451 ns; Loc. = LCFF_X19_Y15_N17; Fanout = 3; REG Node = 'writefifo1:writefifo11\|writefifo1_state.WRITE_UPPART'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "1.569 ns" { clk_syn:inst1|pclk_syn1~clkctrl writefifo1:writefifo11|writefifo1_state.WRITE_UPPART } "NODE_NAME" } "" } } { "writefifo1.v" "" { Text "F:/newboardconfig9/writefifo1.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.636 ns ( 25.36 % ) " "Info: Total cell delay = 1.636 ns ( 25.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.815 ns ( 74.64 % ) " "Info: Total interconnect delay = 4.815 ns ( 74.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "6.451 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl clk_syn:inst1|pclk_syn1 clk_syn:inst1|pclk_syn1~clkctrl writefifo1:writefifo11|writefifo1_state.WRITE_UPPART } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "6.451 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl clk_syn:inst1|pclk_syn1 clk_syn:inst1|pclk_syn1~clkctrl writefifo1:writefifo11|writefifo1_state.WRITE_UPPART } { 0.000ns 1.211ns 0.876ns 1.825ns 0.903ns } { 0.000ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst\|altpll:altpll_component\|_clk0 source 6.451 ns - Shortest register " "Info: - Shortest clock path from clock \"altpll0:inst\|altpll:altpll_component\|_clk0\" to source register is 6.451 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll0:inst\|altpll:altpll_component\|_clk0'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { altpll0:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.211 ns) + CELL(0.000 ns) 1.211 ns altpll0:inst\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 23 " "Info: 2: + IC(1.211 ns) + CELL(0.000 ns) = 1.211 ns; Loc. = CLKCTRL_G3; Fanout = 23; COMB Node = 'altpll0:inst\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "1.211 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.876 ns) + CELL(0.970 ns) 3.057 ns clk_syn:inst1\|pclk_syn1 3 REG LCFF_X16_Y10_N9 2 " "Info: 3: + IC(0.876 ns) + CELL(0.970 ns) = 3.057 ns; Loc. = LCFF_X16_Y10_N9; Fanout = 2; REG Node = 'clk_syn:inst1\|pclk_syn1'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "1.846 ns" { altpll0:inst|altpll:altpll_component|_clk0~clkctrl clk_syn:inst1|pclk_syn1 } "NODE_NAME" } "" } } { "clk_syn.v" "" { Text "F:/newboardconfig9/clk_syn.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.825 ns) + CELL(0.000 ns) 4.882 ns clk_syn:inst1\|pclk_syn1~clkctrl 4 COMB CLKCTRL_G7 35 " "Info: 4: + IC(1.825 ns) + CELL(0.000 ns) = 4.882 ns; Loc. = CLKCTRL_G7; Fanout = 35; COMB Node = 'clk_syn:inst1\|pclk_syn1~clkctrl'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "1.825 ns" { clk_syn:inst1|pclk_syn1 clk_syn:inst1|pclk_syn1~clkctrl } "NODE_NAME" } "" } } { "clk_syn.v" "" { Text "F:/newboardconfig9/clk_syn.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.903 ns) + CELL(0.666 ns) 6.451 ns writefifo1:writefifo11\|writefifo1_state.WRITE_UPPART 5 REG LCFF_X19_Y15_N17 3 " "Info: 5: + IC(0.903 ns) + CELL(0.666 ns) = 6.451 ns; Loc. = LCFF_X19_Y15_N17; Fanout = 3; REG Node = 'writefifo1:writefifo11\|writefifo1_state.WRITE_UPPART'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "1.569 ns" { clk_syn:inst1|pclk_syn1~clkctrl writefifo1:writefifo11|writefifo1_state.WRITE_UPPART } "NODE_NAME" } "" } } { "writefifo1.v" "" { Text "F:/newboardconfig9/writefifo1.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.636 ns ( 25.36 % ) " "Info: Total cell delay = 1.636 ns ( 25.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.815 ns ( 74.64 % ) " "Info: Total interconnect delay = 4.815 ns ( 74.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "6.451 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl clk_syn:inst1|pclk_syn1 clk_syn:inst1|pclk_syn1~clkctrl writefifo1:writefifo11|writefifo1_state.WRITE_UPPART } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "6.451 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl clk_syn:inst1|pclk_syn1 clk_syn:inst1|pclk_syn1~clkctrl writefifo1:writefifo11|writefifo1_state.WRITE_UPPART } { 0.000ns 1.211ns 0.876ns 1.825ns 0.903ns } { 0.000ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "6.451 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl clk_syn:inst1|pclk_syn1 clk_syn:inst1|pclk_syn1~clkctrl writefifo1:writefifo11|writefifo1_state.WRITE_UPPART } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "6.451 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl clk_syn:inst1|pclk_syn1 clk_syn:inst1|pclk_syn1~clkctrl writefifo1:writefifo11|writefifo1_state.WRITE_UPPART } { 0.000ns 1.211ns 0.876ns 1.825ns 0.903ns } { 0.000ns 0.000ns 0.970ns 0.000ns 0.666ns } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "6.451 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl clk_syn:inst1|pclk_syn1 clk_syn:inst1|pclk_syn1~clkctrl writefifo1:writefifo11|writefifo1_state.WRITE_UPPART } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "6.451 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl clk_syn:inst1|pclk_syn1 clk_syn:inst1|pclk_syn1~clkctrl writefifo1:writefifo11|writefifo1_state.WRITE_UPPART } { 0.000ns 1.211ns 0.876ns 1.825ns 0.903ns } { 0.000ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "writefifo1.v" "" { Text "F:/newboardconfig9/writefifo1.v" 47 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "writefifo1.v" "" { Text "F:/newboardconfig9/writefifo1.v" 47 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "6.451 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl clk_syn:inst1|pclk_syn1 clk_syn:inst1|pclk_syn1~clkctrl writefifo1:writefifo11|writefifo1_state.WRITE_UPPART } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "6.451 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl clk_syn:inst1|pclk_syn1 clk_syn:inst1|pclk_syn1~clkctrl writefifo1:writefifo11|writefifo1_state.WRITE_UPPART } { 0.000ns 1.211ns 0.876ns 1.825ns 0.903ns } { 0.000ns 0.000ns 0.970ns 0.000ns 0.666ns } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "6.451 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl clk_syn:inst1|pclk_syn1 clk_syn:inst1|pclk_syn1~clkctrl writefifo1:writefifo11|writefifo1_state.WRITE_UPPART } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "6.451 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl clk_syn:inst1|pclk_syn1 clk_syn:inst1|pclk_syn1~clkctrl writefifo1:writefifo11|writefifo1_state.WRITE_UPPART } { 0.000ns 1.211ns 0.876ns 1.825ns 0.903ns } { 0.000ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboard