newboardconfig.tan.qmsg

cyclone II 208c8编写的 图像采集 显示程序。

{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "altpll0:inst\|altpll:altpll_component\|_clk0 register clk_syn:inst1\|hsyn_syn register writefifo1:writefifo11\|hsyn_pre 10.194 ns " "Info: Slack time is 10.194 ns for clock \"altpll0:inst\|altpll:altpll_component\|_clk0\" between source register \"clk_syn:inst1\|hsyn_syn\" and destination register \"writefifo1:writefifo11\|hsyn_pre\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "11.748 ns + Largest register register " "Info: + Largest register to register requirement is 11.748 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "8.333 ns + " "Info: + Setup relationship between source and destination is 8.333 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 6.043 ns " "Info: + Latch edge is 6.043 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination altpll0:inst\|altpll:altpll_component\|_clk0 16.666 ns 6.043 ns inverted 50 " "Info: Clock period of Destination clock \"altpll0:inst\|altpll:altpll_component\|_clk0\" is 16.666 ns with inverted offset of 6.043 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.290 ns " "Info: - Launch edge is -2.290 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source altpll0:inst\|altpll:altpll_component\|_clk0 16.666 ns -2.290 ns  50 " "Info: Clock period of Source clock \"altpll0:inst\|altpll:altpll_component\|_clk0\" is 16.666 ns with  offset of -2.290 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "3.679 ns + Largest " "Info: + Largest clock skew is 3.679 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst\|altpll:altpll_component\|_clk0 destination 6.443 ns + Shortest register " "Info: + Shortest clock path from clock \"altpll0:inst\|altpll:altpll_component\|_clk0\" to destination register is 6.443 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll0:inst\|altpll:altpll_component\|_clk0'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { altpll0:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.211 ns) + CELL(0.000 ns) 1.211 ns altpll0:inst\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 23 " "Info: 2: + IC(1.211 ns) + CELL(0.000 ns) = 1.211 ns; Loc. = CLKCTRL_G3; Fanout = 23; COMB Node = 'altpll0:inst\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "1.211 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.876 ns) + CELL(0.970 ns) 3.057 ns clk_syn:inst1\|pclk_syn1 3 REG LCFF_X16_Y10_N9 2 " "Info: 3: + IC(0.876 ns) + CELL(0.970 ns) = 3.057 ns; Loc. = LCFF_X16_Y10_N9; Fanout = 2; REG Node = 'clk_syn:inst1\|pclk_syn1'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "1.846 ns" { altpll0:inst|altpll:altpll_component|_clk0~clkctrl clk_syn:inst1|pclk_syn1 } "NODE_NAME" } "" } } { "clk_syn.v" "" { Text "F:/newboardconfig9/clk_syn.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.825 ns) + CELL(0.000 ns) 4.882 ns clk_syn:inst1\|pclk_syn1~clkctrl 4 COMB CLKCTRL_G7 35 " "Info: 4: + IC(1.825 ns) + CELL(0.000 ns) = 4.882 ns; Loc. = CLKCTRL_G7; Fanout = 35; COMB Node = 'clk_syn:inst1\|pclk_syn1~clkctrl'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "1.825 ns" { clk_syn:inst1|pclk_syn1 clk_syn:inst1|pclk_syn1~clkctrl } "NODE_NAME" } "" } } { "clk_syn.v" "" { Text "F:/newboardconfig9/clk_syn.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.895 ns) + CELL(0.666 ns) 6.443 ns writefifo1:writefifo11\|hsyn_pre 5 REG LCFF_X21_Y7_N19 1 " "Info: 5: + IC(0.895 ns) + CELL(0.666 ns) = 6.443 ns; Loc. = LCFF_X21_Y7_N19; Fanout = 1; REG Node = 'writefifo1:writefifo11\|hsyn_pre'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "1.561 ns" { clk_syn:inst1|pclk_syn1~clkctrl writefifo1:writefifo11|hsyn_pre } "NODE_NAME" } "" } } { "writefifo1.v" "" { Text "F:/newboardconfig9/writefifo1.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.636 ns ( 25.39 % ) " "Info: Total cell delay = 1.636 ns ( 25.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.807 ns ( 74.61 % ) " "Info: Total interconnect delay = 4.807 ns ( 74.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "6.443 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl clk_syn:inst1|pclk_syn1 clk_syn:inst1|pclk_syn1~clkctrl writefifo1:writefifo11|hsyn_pre } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "6.443 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl clk_syn:inst1|pclk_syn1 clk_syn:inst1|pclk_syn1~clkctrl writefifo1:writefifo11|hsyn_pre } { 0.000ns 1.211ns 0.876ns 1.825ns 0.895ns } { 0.000ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst\|altpll:altpll_component\|_clk0 source 2.764 ns - Longest register " "Info: - Longest clock path from clock \"altpll0:inst\|altpll:altpll_component\|_clk0\" to source register is 2.764 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll0:inst\|altpll:altpll_component\|_clk0'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { altpll0:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.211 ns) + CELL(0.000 ns) 1.211 ns altpll0:inst\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 23 " "Info: 2: + IC(1.211 ns) + CELL(0.000 ns) = 1.211 ns; Loc. = CLKCTRL_G3; Fanout = 23; COMB Node = 'altpll0:inst\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "1.211 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.887 ns) + CELL(0.666 ns) 2.764 ns clk_syn:inst1\|hsyn_syn 3 REG LCFF_X19_Y7_N5 2 " "Info: 3: + IC(0.887 ns) + CELL(0.666 ns) = 2.764 ns; Loc. = LCFF_X19_Y7_N5; Fanout = 2; REG Node = 'clk_syn:inst1\|hsyn_syn'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "1.553 ns" { altpll0:inst|altpll:altpll_component|_clk0~clkctrl clk_syn:inst1|hsyn_syn } "NODE_NAME" } "" } } { "clk_syn.v" "" { Text "F:/newboardconfig9/clk_syn.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 24.10 % ) " "Info: Total cell delay = 0.666 ns ( 24.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.098 ns ( 75.90 % ) " "Info: Total interconnect delay = 2.098 ns ( 75.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "2.764 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl clk_syn:inst1|hsyn_syn } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "2.764 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl clk_syn:inst1|hsyn_syn } { 0.000ns 1.211ns 0.887ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "6.443 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl clk_syn:inst1|pclk_syn1 clk_syn:inst1|pclk_syn1~clkctrl writefifo1:writefifo11|hsyn_pre } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "6.443 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl clk_syn:inst1|pclk_syn1 clk_syn:inst1|pclk_syn1~clkctrl writefifo1:writefifo11|hsyn_pre } { 0.000ns 1.211ns 0.876ns 1.825ns 0.895ns } { 0.000ns 0.000ns 0.970ns 0.000ns 0.666ns } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "2.764 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl clk_syn:inst1|hsyn_syn } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "2.764 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl clk_syn:inst1|hsyn_syn } { 0.000ns 1.211ns 0.887ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "clk_syn.v" "" { Text "F:/newboardconfig9/clk_syn.v" 24 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns - " "Info: - Micro setup delay of destination is -0.040 ns" {  } { { "writefifo1.v" "" { Text "F:/newboardconfig9/writefifo1.v" 41 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "6.443 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl clk_syn:inst1|pclk_syn1 clk_syn:inst1|pclk_syn1~clkctrl writefifo1:writefifo11|hsyn_pre } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "6.443 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl clk_syn:inst1|pclk_syn1 clk_syn:inst1|pclk_syn1~clkctrl writefifo1:writefifo11|hsyn_pre } { 0.000ns 1.211ns 0.876ns 1.825ns 0.895ns } { 0.000ns 0.000ns 0.970ns 0.000ns 0.666ns } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "2.764 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl clk_syn:inst1|hsyn_syn } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "2.764 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl clk_syn:inst1|hsyn_syn } { 0.000ns 1.211ns 0.887ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.554 ns - Longest register register " "Info: - Longest register to register delay is 1.554 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_syn:inst1\|hsyn_syn 1 REG LCFF_X19_Y7_N5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y7_N5; Fanout = 2; REG Node = 'clk_syn:inst1\|hsyn_syn'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { clk_syn:inst1|hsyn_syn } "NODE_NAME" } "" } } { "clk_syn.v" "" { Text "F:/newboardconfig9/clk_syn.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.094 ns) + CELL(0.460 ns) 1.554 ns writefifo1:writefifo11\|hsyn_pre 2 REG LCFF_X21_Y7_N19 1 " "Info: 2: + IC(1.094 ns) + CELL(0.460 ns) = 1.554 ns; Loc. = LCFF_X21_Y7_N19; Fanout = 1; REG Node = 'writefifo1:writefifo11\|hsyn_pre'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "1.554 ns" { clk_syn:inst1|hsyn_syn writefifo1:writefifo11|hsyn_pre } "NODE_NAME" } "" } } { "writefifo1.v" "" { Text "F:/newboardconfig9/writefifo1.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.460 ns ( 29.60 % ) " "Info: Total cell delay = 0.460 ns ( 29.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.094 ns ( 70.40 % ) " "Info: Total interconnect delay = 1.094 ns ( 70.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "1.554 ns" { clk_syn:inst1|hsyn_syn writefifo1:writefifo11|hsyn_pre } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "1.554 ns" { clk_syn:inst1|hsyn_syn writefifo1:writefifo11|hsyn_pre } { 0.000ns 1.094ns } { 0.000ns 0.460ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "6.443 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl clk_syn:inst1|pclk_syn1 clk_syn:inst1|pclk_syn1~clkctrl writefifo1:writefifo11|hsyn_pre } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "6.443 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl clk_syn:inst1|pclk_syn1 clk_syn:inst1|pclk_syn1~clkctrl writefifo1:writefifo11|hsyn_pre } { 0.000ns 1.211ns 0.876ns 1.825ns 0.895ns } { 0.000ns 0.000ns 0.970ns 0.000ns 0.666ns } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "2.764 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl clk_syn:inst1|hsyn_syn } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "2.764 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl clk_syn:inst1|hsyn_syn } { 0.000ns 1.211ns 0.887ns } { 0.000ns 0.000ns 0.666ns } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "1.554 ns" { clk_syn:inst1|hsyn_syn writefifo1:writefifo11|hsyn_pre } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "1.554 ns" { clk_syn:inst1|hsyn_syn writefifo1:writefifo11|hsyn_pre } { 0.000ns 1.094ns } { 0.000ns 0.460ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "fpgaclk " "Info: No valid register-to-register data paths exist for clock \"fpgaclk\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}