📄 mux_lib.tdf
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--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_SIZE=8 LPM_WIDTH=4 LPM_WIDTHS=3 data result sel
--VERSION_BEGIN 5.1 cbx_lpm_mux 2005:04:28:09:25:00:SJ cbx_mgl 2005:10:09:07:39:04:SJ VERSION_END
-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--synthesis_resources = lut 20
SUBDESIGN mux_lib
(
data[31..0] : input;
result[3..0] : output;
sel[2..0] : input;
)
VARIABLE
result_node[3..0] : WIRE;
sel_ffs_wire[2..0] : WIRE;
sel_node[2..0] : WIRE;
w_data473w[7..0] : WIRE;
w_data495w[3..0] : WIRE;
w_data496w[3..0] : WIRE;
w_data544w[7..0] : WIRE;
w_data566w[3..0] : WIRE;
w_data567w[3..0] : WIRE;
w_data613w[7..0] : WIRE;
w_data635w[3..0] : WIRE;
w_data636w[3..0] : WIRE;
w_data682w[7..0] : WIRE;
w_data704w[3..0] : WIRE;
w_data705w[3..0] : WIRE;
w_result493w : WIRE;
w_result494w : WIRE;
w_result501w : WIRE;
w_result522w : WIRE;
w_result564w : WIRE;
w_result565w : WIRE;
w_result572w : WIRE;
w_result593w : WIRE;
w_result633w : WIRE;
w_result634w : WIRE;
w_result641w : WIRE;
w_result662w : WIRE;
w_result702w : WIRE;
w_result703w : WIRE;
w_result710w : WIRE;
w_result731w : WIRE;
w_sel497w[1..0] : WIRE;
w_sel568w[1..0] : WIRE;
w_sel637w[1..0] : WIRE;
w_sel706w[1..0] : WIRE;
BEGIN
result[] = result_node[];
result_node[] = ( ((sel_node[2..2] & w_result703w) # ((! sel_node[2..2]) & w_result702w)), ((sel_node[2..2] & w_result634w) # ((! sel_node[2..2]) & w_result633w)), ((sel_node[2..2] & w_result565w) # ((! sel_node[2..2]) & w_result564w)), ((sel_node[2..2] & w_result494w) # ((! sel_node[2..2]) & w_result493w)));
sel_ffs_wire[] = ( sel[2..0]);
sel_node[] = ( sel_ffs_wire[2..2], sel[1..0]);
w_data473w[] = ( data[28..28], data[24..24], data[20..20], data[16..16], data[12..12], data[8..8], data[4..4], data[0..0]);
w_data495w[3..0] = w_data473w[3..0];
w_data496w[3..0] = w_data473w[7..4];
w_data544w[] = ( data[29..29], data[25..25], data[21..21], data[17..17], data[13..13], data[9..9], data[5..5], data[1..1]);
w_data566w[3..0] = w_data544w[3..0];
w_data567w[3..0] = w_data544w[7..4];
w_data613w[] = ( data[30..30], data[26..26], data[22..22], data[18..18], data[14..14], data[10..10], data[6..6], data[2..2]);
w_data635w[3..0] = w_data613w[3..0];
w_data636w[3..0] = w_data613w[7..4];
w_data682w[] = ( data[31..31], data[27..27], data[23..23], data[19..19], data[15..15], data[11..11], data[7..7], data[3..3]);
w_data704w[3..0] = w_data682w[3..0];
w_data705w[3..0] = w_data682w[7..4];
w_result493w = (((w_data495w[1..1] & w_sel497w[0..0]) & (! w_result501w)) # (w_result501w & (w_data495w[3..3] # (! w_sel497w[0..0]))));
w_result494w = (((w_data496w[1..1] & w_sel497w[0..0]) & (! w_result522w)) # (w_result522w & (w_data496w[3..3] # (! w_sel497w[0..0]))));
w_result501w = (((w_data495w[0..0] & (! w_sel497w[1..1])) & (! w_sel497w[0..0])) # (w_sel497w[1..1] & (w_sel497w[0..0] # w_data495w[2..2])));
w_result522w = (((w_data496w[0..0] & (! w_sel497w[1..1])) & (! w_sel497w[0..0])) # (w_sel497w[1..1] & (w_sel497w[0..0] # w_data496w[2..2])));
w_result564w = (((w_data566w[1..1] & w_sel568w[0..0]) & (! w_result572w)) # (w_result572w & (w_data566w[3..3] # (! w_sel568w[0..0]))));
w_result565w = (((w_data567w[1..1] & w_sel568w[0..0]) & (! w_result593w)) # (w_result593w & (w_data567w[3..3] # (! w_sel568w[0..0]))));
w_result572w = (((w_data566w[0..0] & (! w_sel568w[1..1])) & (! w_sel568w[0..0])) # (w_sel568w[1..1] & (w_sel568w[0..0] # w_data566w[2..2])));
w_result593w = (((w_data567w[0..0] & (! w_sel568w[1..1])) & (! w_sel568w[0..0])) # (w_sel568w[1..1] & (w_sel568w[0..0] # w_data567w[2..2])));
w_result633w = (((w_data635w[1..1] & w_sel637w[0..0]) & (! w_result641w)) # (w_result641w & (w_data635w[3..3] # (! w_sel637w[0..0]))));
w_result634w = (((w_data636w[1..1] & w_sel637w[0..0]) & (! w_result662w)) # (w_result662w & (w_data636w[3..3] # (! w_sel637w[0..0]))));
w_result641w = (((w_data635w[0..0] & (! w_sel637w[1..1])) & (! w_sel637w[0..0])) # (w_sel637w[1..1] & (w_sel637w[0..0] # w_data635w[2..2])));
w_result662w = (((w_data636w[0..0] & (! w_sel637w[1..1])) & (! w_sel637w[0..0])) # (w_sel637w[1..1] & (w_sel637w[0..0] # w_data636w[2..2])));
w_result702w = (((w_data704w[1..1] & w_sel706w[0..0]) & (! w_result710w)) # (w_result710w & (w_data704w[3..3] # (! w_sel706w[0..0]))));
w_result703w = (((w_data705w[1..1] & w_sel706w[0..0]) & (! w_result731w)) # (w_result731w & (w_data705w[3..3] # (! w_sel706w[0..0]))));
w_result710w = (((w_data704w[0..0] & (! w_sel706w[1..1])) & (! w_sel706w[0..0])) # (w_sel706w[1..1] & (w_sel706w[0..0] # w_data704w[2..2])));
w_result731w = (((w_data705w[0..0] & (! w_sel706w[1..1])) & (! w_sel706w[0..0])) # (w_sel706w[1..1] & (w_sel706w[0..0] # w_data705w[2..2])));
w_sel497w[1..0] = sel_node[1..0];
w_sel568w[1..0] = sel_node[1..0];
w_sel637w[1..0] = sel_node[1..0];
w_sel706w[1..0] = sel_node[1..0];
END;
--VALID FILE
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