newboardconfig.fit.qmsg

cyclone II 208c8编写的 图像采集 显示程序。

{ "Warning" "WDAT_PRELIMINARY_TIMING" "EP2C8Q208C8 " "Warning: Timing characteristics of device EP2C8Q208C8 are preliminary" {  } {  } 0 0 "Timing characteristics of device %1!s! are preliminary" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "50 " "Warning: Found 50 output pins without output pin load capacitance assignment" { { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "R8019en 0 " "Warning: Pin \"R8019en\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "dspready 0 " "Warning: Pin \"dspready\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "fifo1we 0 " "Warning: Pin \"fifo1we\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "fifo1wrst 0 " "Warning: Pin \"fifo1wrst\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "cmosreset 0 " "Warning: Pin \"cmosreset\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "pwdn 0 " "Warning: Pin \"pwdn\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "fifo1re 0 " "Warning: Pin \"fifo1re\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "fifo1oe 0 " "Warning: Pin \"fifo1oe\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "fifo1rrst 0 " "Warning: Pin \"fifo1rrst\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "fifo1rclk 0 " "Warning: Pin \"fifo1rclk\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "fifo1wclk 0 " "Warning: Pin \"fifo1wclk\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "blank 0 " "Warning: Pin \"blank\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "vga_clk 0 " "Warning: Pin \"vga_clk\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "vga_hsyn 0 " "Warning: Pin \"vga_hsyn\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "fifo1data\[7\] 0 " "Warning: Pin \"fifo1data\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "fifo1data\[6\] 0 " "Warning: Pin \"fifo1data\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "fifo1data\[5\] 0 " "Warning: Pin \"fifo1data\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "fifo1data\[4\] 0 " "Warning: Pin \"fifo1data\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "fifo1data\[3\] 0 " "Warning: Pin \"fifo1data\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "fifo1data\[2\] 0 " "Warning: Pin \"fifo1data\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "fifo1data\[1\] 0 " "Warning: Pin \"fifo1data\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "fifo1data\[0\] 0 " "Warning: Pin \"fifo1data\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "fifo1s\[2\] 0 " "Warning: Pin \"fifo1s\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "fifo1s\[1\] 0 " "Warning: Pin \"fifo1s\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "fifo1s\[0\] 0 " "Warning: Pin \"fifo1s\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "fifo2s\[2\] 0 " "Warning: Pin \"fifo2s\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "fifo2s\[1\] 0 " "Warning: Pin \"fifo2s\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "fifo2s\[0\] 0 " "Warning: Pin \"fifo2s\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "flashaddr\[19\] 0 " "Warning: Pin \"flashaddr\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "flashaddr\[18\] 0 " "Warning: Pin \"flashaddr\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "flashaddr\[17\] 0 " "Warning: Pin \"flashaddr\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "flashaddr\[16\] 0 " "Warning: Pin \"flashaddr\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "flashaddr\[15\] 0 " "Warning: Pin \"flashaddr\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "flashaddr\[14\] 0 " "Warning: Pin \"flashaddr\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "uv\[7\] 0 " "Warning: Pin \"uv\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "uv\[6\] 0 " "Warning: Pin \"uv\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "uv\[5\] 0 " "Warning: Pin \"uv\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "uv\[4\] 0 " "Warning: Pin \"uv\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "uv\[3\] 0 " "Warning: Pin \"uv\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "uv\[2\] 0 " "Warning: Pin \"uv\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "uv\[1\] 0 " "Warning: Pin \"uv\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "uv\[0\] 0 " "Warning: Pin \"uv\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "y\[7\] 0 " "Warning: Pin \"y\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "y\[6\] 0 " "Warning: Pin \"y\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "y\[5\] 0 " "Warning: Pin \"y\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "y\[4\] 0 " "Warning: Pin \"y\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "y\[3\] 0 " "Warning: Pin \"y\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "y\[2\] 0 " "Warning: Pin \"y\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "y\[1\] 0 " "Warning: Pin \"y\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "y\[0\] 0 " "Warning: Pin \"y\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "17 " "Warning: Following 17 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "dspready VCC " "Info: Pin dspready has VCC driving its datain port" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 192 360 536 208 "dspready" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "dspready" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { dspready } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { dspready } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "pwdn GND " "Info: Pin pwdn has GND driving its datain port" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { -224 280 456 -208 "pwdn" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "pwdn" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { pwdn } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { pwdn } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "blank GND " "Info: Pin blank has GND driving its datain port" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 968 -200 -24 984 "blank" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "blank" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { blank } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { blank } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "vga_clk GND " "Info: Pin vga_clk has GND driving its datain port" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 1008 -200 -24 1024 "vga_clk" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "vga_clk" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { vga_clk } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { vga_clk } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "vga_hsyn GND " "Info: Pin vga_hsyn has GND driving its datain port" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 936 -200 -24 952 "vga_hsyn" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "vga_hsyn" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { vga_hsyn } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { vga_hsyn } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "fifo1s\[2\] VCC " "Info: Pin fifo1s\[2\] has VCC driving its datain port" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 400 1136 1312 416 "fifo1s\[2..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fifo1s\[2\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { fifo1s[2] } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { fifo1s[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "fifo1s\[1\] VCC " "Info: Pin fifo1s\[1\] has VCC driving its datain port" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 400 1136 1312 416 "fifo1s\[2..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fifo1s\[1\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { fifo1s[1] } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { fifo1s[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "fifo1s\[0\] VCC " "Info: Pin fifo1s\[0\] has VCC driving its datain port" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 400 1136 1312 416 "fifo1s\[2..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fifo1s\[0\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { fifo1s[0] } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { fifo1s[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "fifo2s\[2\] VCC " "Info: Pin fifo2s\[2\] has VCC driving its datain port" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 48 312 488 64 "fifo2s\[2..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fifo2s\[2\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { fifo2s[2] } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { fifo2s[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "fifo2s\[1\] VCC " "Info: Pin fifo2s\[1\] has VCC driving its datain port" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 48 312 488 64 "fifo2s\[2..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fifo2s\[1\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { fifo2s[1] } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { fifo2s[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "fifo2s\[0\] VCC " "Info: Pin fifo2s\[0\] has VCC driving its datain port" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 48 312 488 64 "fifo2s\[2..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fifo2s\[0\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { fifo2s[0] } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { fifo2s[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "flashaddr\[19\] GND " "Info: Pin flashaddr\[19\] has GND driving its datain port" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 64 312 488 80 "flashaddr\[19..14\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "flashaddr\[19\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { flashaddr[19] } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { flashaddr[19] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "flashaddr\[18\] GND " "Info: Pin flashaddr\[18\] has GND driving its datain port" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 64 312 488 80 "flashaddr\[19..14\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "flashaddr\[18\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { flashaddr[18] } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { flashaddr[18] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "flashaddr\[17\] GND " "Info: Pin flashaddr\[17\] has GND driving its datain port" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 64 312 488 80 "flashaddr\[19..14\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "flashaddr\[17\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { flashaddr[17] } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { flashaddr[17] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "flashaddr\[16\] GND " "Info: Pin flashaddr\[16\] has GND driving its datain port" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 64 312 488 80 "flashaddr\[19..14\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "flashaddr\[16\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { flashaddr[16] } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { flashaddr[16] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "flashaddr\[15\] GND " "Info: Pin flashaddr\[15\] has GND driving its datain port" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 64 312 488 80 "flashaddr\[19..14\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "flashaddr\[15\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { flashaddr[15] } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { flashaddr[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "flashaddr\[14\] GND " "Info: Pin flashaddr\[14\] has GND driving its datain port" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 64 312 488 80 "flashaddr\[19..14\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "flashaddr\[14\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { flashaddr[14] } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { flashaddr[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IFSAC_FSAC_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP" "resetcmos:resetcmos1\|reset_gen:comsreset1\|rst_cnt\[17\] (inverted) " "Info: Following pins have the same output enable: resetcmos:resetcmos1\|reset_gen:comsreset1\|rst_cnt\[17\] (inverted)" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional uv\[7\] LVTTL " "Info: Type bidirectional pin uv\[7\] uses the LVTTL I/O standard" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 448 1136 1312 464 "uv\[7..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "uv\[7\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { uv[7] } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { uv[7] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional uv\[6\] LVTTL " "Info: Type bidirectional pin uv\[6\] uses the LVTTL I/O standard" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 448 1136 1312 464 "uv\[7..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "uv\[6\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { uv[6] } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { uv[6] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional uv\[5\] LVTTL " "Info: Type bidirectional pin uv\[5\] uses the LVTTL I/O standard" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 448 1136 1312 464 "uv\[7..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "uv\[5\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { uv[5] } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { uv[5] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional uv\[4\] LVTTL " "Info: Type bidirectional pin uv\[4\] uses the LVTTL I/O standard" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 448 1136 1312 464 "uv\[7..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "uv\[4\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { uv[4] } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { uv[4] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional uv\[3\] LVTTL " "Info: Type bidirectional pin uv\[3\] uses the LVTTL I/O standard" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 448 1136 1312 464 "uv\[7..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "uv\[3\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { uv[3] } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { uv[3] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional uv\[2\] LVTTL " "Info: Type bidirectional pin uv\[2\] uses the LVTTL I/O standard" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 448 1136 1312 464 "uv\[7..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "uv\[2\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { uv[2] } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { uv[2] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional uv\[1\] LVTTL " "Info: Type bidirectional pin uv\[1\] uses the LVTTL I/O standard" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 448 1136 1312 464 "uv\[7..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "uv\[1\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { uv[1] } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { uv[1] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional uv\[0\] LVTTL " "Info: Type bidirectional pin uv\[0\] uses the LVTTL I/O standard" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 448 1136 1312 464 "uv\[7..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "uv\[0\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { uv[0] } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { uv[0] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional y\[7\] LVTTL " "Info: Type bidirectional pin y\[7\] uses the LVTTL I/O standard" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 432 1136 1312 448 "y\[7..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "y\[7\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { y[7] } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { y[7] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional y\[6\] LVTTL " "Info: Type bidirectional pin y\[6\] uses the LVTTL I/O standard" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 432 1136 1312 448 "y\[7..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "y\[6\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { y[6] } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { y[6] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional y\[5\] LVTTL " "Info: Type bidirectional pin y\[5\] uses the LVTTL I/O standard" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 432 1136 1312 448 "y\[7..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "y\[5\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { y[5] } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { y[5] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional y\[4\] LVTTL " "Info: Type bidirectional pin y\[4\] uses the LVTTL I/O standard" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 432 1136 1312 448 "y\[7..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "y\[4\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { y[4] } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { y[4] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional y\[3\] LVTTL " "Info: Type bidirectional pin y\[3\] uses the LVTTL I/O standard" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 432 1136 1312 448 "y\[7..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "y\[3\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { y[3] } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { y[3] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional y\[2\] LVTTL " "Info: Type bidirectional pin y\[2\] uses the LVTTL I/O standard" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 432 1136 1312 448 "y\[7..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "y\[2\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN"