newboardconfig.fit.qmsg

cyclone II 208c8编写的 图像采集 显示程序。

{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "1.399 ns register register " "Info: Estimated most critical path is register to register delay of 1.399 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_syn:inst1\|hsyn_syn 1 REG LAB_X19_Y7 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X19_Y7; Fanout = 2; REG Node = 'clk_syn:inst1\|hsyn_syn'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { clk_syn:inst1|hsyn_syn } "NODE_NAME" } "" } } { "clk_syn.v" "" { Text "F:/newboardconfig9/clk_syn.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.291 ns) + CELL(0.108 ns) 1.399 ns writefifo1:writefifo11\|hsyn_pre 2 REG LAB_X21_Y7 1 " "Info: 2: + IC(1.291 ns) + CELL(0.108 ns) = 1.399 ns; Loc. = LAB_X21_Y7; Fanout = 1; REG Node = 'writefifo1:writefifo11\|hsyn_pre'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "1.399 ns" { clk_syn:inst1|hsyn_syn writefifo1:writefifo11|hsyn_pre } "NODE_NAME" } "" } } { "writefifo1.v" "" { Text "F:/newboardconfig9/writefifo1.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.108 ns ( 7.72 % ) " "Info: Total cell delay = 0.108 ns ( 7.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.291 ns ( 92.28 % ) " "Info: Total interconnect delay = 1.291 ns ( 92.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "1.399 ns" { clk_syn:inst1|hsyn_syn writefifo1:writefifo11|hsyn_pre } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 1 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%" {  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}