newboardconfig.fit.qmsg

cyclone II 208c8编写的 图像采集 显示程序。

{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altpll0:inst\|altpll:altpll_component\|_clk0 (placed in counter C0 of PLL_1) " "Info: Automatically promoted node altpll0:inst\|altpll:altpll_component\|_clk0 (placed in counter C0 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0}  } { { "altpll.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "altpll0:inst\|altpll:altpll_component\|_clk0" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { altpll0:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { altpll0:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_syn:inst1\|pclk_syn1  " "Info: Automatically promoted node clk_syn:inst1\|pclk_syn1 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fifo1wclk " "Info: Destination node fifo1wclk" {  } { { "newboardconfig.bdf" "" { Schematic "F:/newboardconfig9/newboardconfig.bdf" { { 352 1136 1312 368 "fifo1wclk" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fifo1wclk" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { fifo1wclk } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { fifo1wclk } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0}  } { { "clk_syn.v" "" { Text "F:/newboardconfig9/clk_syn.v" 24 -1 0 } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk_syn:inst1\|pclk_syn1" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { clk_syn:inst1|pclk_syn1 } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { clk_syn:inst1|pclk_syn1 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "dsp:dsp1\|cmosrstport~55  " "Info: Automatically promoted node dsp:dsp1\|cmosrstport~55 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0}  } { { "dsp.v" "" { Text "F:/newboardconfig9/dsp.v" 28 -1 0 } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "dsp:dsp1\|cmosrstport~55" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { dsp:dsp1|cmosrstport~55 } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { dsp:dsp1|cmosrstport~55 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "dsp:dsp1\|fifo1wrrstport~4  " "Info: Automatically promoted node dsp:dsp1\|fifo1wrrstport~4 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "writefifo1:writefifo11\|fifo1wrst_reg~165 " "Info: Destination node writefifo1:writefifo11\|fifo1wrst_reg~165" {  } { { "writefifo1.v" "" { Text "F:/newboardconfig9/writefifo1.v" 189 -1 0 } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "writefifo1:writefifo11\|fifo1wrst_reg~165" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { writefifo1:writefifo11|fifo1wrst_reg~165 } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { writefifo1:writefifo11|fifo1wrst_reg~165 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0}  } { { "dsp.v" "" { Text "F:/newboardconfig9/dsp.v" 28 -1 0 } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "dsp:dsp1\|fifo1wrrstport~4" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "newboardconfig" "UNKNOWN" "V1" "F:/newboardconfig9/db/newboardconfig.quartus_db" { Floorplan "F:/newboardconfig9/" "" "" { dsp:dsp1|fifo1wrrstport~4 } "NODE_NAME" } "" } } { "F:/newboardconfig9/newboardconfig.fld" "" { Floorplan "F:/newboardconfig9/newboardconfig.fld" "" "" { dsp:dsp1|fifo1wrrstport~4 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0 0 "Started Fast Input/Output/OE register processing" 0 0}