📄 mux_hib.tdf
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--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_SIZE=4 LPM_WIDTH=5 LPM_WIDTHS=2 data result sel
--VERSION_BEGIN 5.1 cbx_lpm_mux 2005:04:28:09:25:00:SJ cbx_mgl 2005:10:09:07:39:04:SJ VERSION_END
-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--synthesis_resources = lut 10
SUBDESIGN mux_hib
(
data[19..0] : input;
result[4..0] : output;
sel[1..0] : input;
)
VARIABLE
result_node[4..0] : WIRE;
sel_node[1..0] : WIRE;
w_data332w[3..0] : WIRE;
w_data362w[3..0] : WIRE;
w_data387w[3..0] : WIRE;
w_data412w[3..0] : WIRE;
w_data437w[3..0] : WIRE;
w_result344w : WIRE;
w_result374w : WIRE;
w_result399w : WIRE;
w_result424w : WIRE;
w_result449w : WIRE;
BEGIN
result[] = result_node[];
result_node[] = ( (((w_data437w[1..1] & sel_node[0..0]) & (! w_result449w)) # (w_result449w & (w_data437w[3..3] # (! sel_node[0..0])))), (((w_data412w[1..1] & sel_node[0..0]) & (! w_result424w)) # (w_result424w & (w_data412w[3..3] # (! sel_node[0..0])))), (((w_data387w[1..1] & sel_node[0..0]) & (! w_result399w)) # (w_result399w & (w_data387w[3..3] # (! sel_node[0..0])))), (((w_data362w[1..1] & sel_node[0..0]) & (! w_result374w)) # (w_result374w & (w_data362w[3..3] # (! sel_node[0..0])))), (((w_data332w[1..1] & sel_node[0..0]) & (! w_result344w)) # (w_result344w & (w_data332w[3..3] # (! sel_node[0..0])))));
sel_node[] = ( sel[1..0]);
w_data332w[] = ( data[15..15], data[10..10], data[5..5], data[0..0]);
w_data362w[] = ( data[16..16], data[11..11], data[6..6], data[1..1]);
w_data387w[] = ( data[17..17], data[12..12], data[7..7], data[2..2]);
w_data412w[] = ( data[18..18], data[13..13], data[8..8], data[3..3]);
w_data437w[] = ( data[19..19], data[14..14], data[9..9], data[4..4]);
w_result344w = (((w_data332w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data332w[2..2])));
w_result374w = (((w_data362w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data362w[2..2])));
w_result399w = (((w_data387w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data387w[2..2])));
w_result424w = (((w_data412w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data412w[2..2])));
w_result449w = (((w_data437w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data437w[2..2])));
END;
--VALID FILE
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