stp2.stp

cyclone II 208c8编写的 图像采集 显示程序。

<session jtag_chain="ByteBlasterII on 192.168.1.36 [LPT1]" jtag_device="@1: EP2C8 (0x020B20DD)" sof_file="">
  <display_tree gui_logging_enabled="0">
    <display_branch instance="auto_signaltap_0" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
  </display_tree>
  <instance entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
    <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="3"/>
    <signal_set global_temp="1" is_expanded="true" name="signal_set: 2008/01/03 19:33:46  #0">
      <clock name="writefifo1:writefifo11|pclk" polarity="posedge"/>
      <config ram_type="M4K" reserved_data_nodes="0" reserved_trigger_nodes="0" sample_depth="4096" trigger_in_enable="yes" trigger_in_node="writefifo1:writefifo11|frdata_valid" trigger_out_enable="no"/>
      <top_entity/>
      <signal_vec>
        <trigger_input_vec>
          <wire connection_status="true" name="writefifo1:writefifo11|frdata_valid" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|hdata_valid" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[0]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[10]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[11]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[12]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[13]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[14]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[15]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[16]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[17]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[18]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[19]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[1]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[2]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[3]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[4]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[5]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[6]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[7]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[8]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[9]" tap_mode="classic" type="register"/>
        </trigger_input_vec>
        <data_input_vec>
          <wire connection_status="true" name="writefifo1:writefifo11|frdata_valid" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|hdata_valid" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[0]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[10]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[11]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[12]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[13]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[14]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[15]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[16]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[17]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[18]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[19]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[1]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[2]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[3]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[4]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[5]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[6]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[7]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[8]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="writefifo1:writefifo11|pixl_cnt[9]" tap_mode="classic" type="register"/>
        </data_input_vec>
      </signal_vec>
      <presentation>
        <data_view>
          <net is_signal_inverted="no" name="writefifo1:writefifo11|frdata_valid"/>
          <net is_signal_inverted="no" name="writefifo1:writefifo11|hdata_valid"/>
          <bus is_signal_inverted="no" link="all" name="writefifo1:writefifo11|pixl_cnt" order="msb_to_lsb" radix="hex" state="collapse" type="register">
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[19]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[18]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[17]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[16]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[15]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[14]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[13]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[12]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[11]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[10]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[9]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[8]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[7]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[6]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[5]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[4]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[3]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[2]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[1]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[0]"/>
          </bus>
        </data_view>
        <setup_view>
          <net is_signal_inverted="no" name="writefifo1:writefifo11|frdata_valid"/>
          <net is_signal_inverted="no" name="writefifo1:writefifo11|hdata_valid"/>
          <bus is_signal_inverted="no" link="all" name="writefifo1:writefifo11|pixl_cnt" order="msb_to_lsb" radix="hex" state="collapse" type="register">
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[19]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[18]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[17]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[16]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[15]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[14]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[13]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[12]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[11]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[10]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[9]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[8]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[7]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[6]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[5]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[4]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[3]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[2]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[1]"/>
            <net is_signal_inverted="no" name="writefifo1:writefifo11|pixl_cnt[0]"/>
          </bus>
        </setup_view>
      </presentation>
      <trigger global_temp="1" is_expanded="true" name="trigger: 2008/01/03 19:33:46  #1" position="pre" segment_size="1" trigger_in="falling edge" trigger_out="active high" trigger_type="circular">
        <events>
          <level enabled="yes" type="basic">
            <op_node/>
          </level>
        </events>
      </trigger>
    </signal_set>
    <position_info>
      <single attribute="active tab" value="1"/>
      <single attribute="data horizontal scroll position" value="869"/>
      <single attribute="data vertical scroll position" value="0"/>
      <single attribute="setup horizontal scroll position" value="45"/>
      <single attribute="setup vertical scroll position" value="0"/>
      <single attribute="zoom level denominator" value="1"/>
      <single attribute="zoom level numerator" value="4"/>
      <single attribute="zoom offset denominator" value="1"/>
      <single attribute="zoom offset numerator" value="30720"/>
    </position_info>
  </instance>
  <mnemonics/>
  <global_info>
    <single attribute="active instance" value="0"/>
    <multi attribute="column width" size="18" value="34,34,166,74,68,70,88,100,101,101,101,101,101,101,101,101,107,78"/>
    <multi attribute="window position" size="9" value="989,492,398,124,356,50,0,0,0"/>
  </global_info>
</session>