newboardconfig.tan.rpt

cyclone II 208c8编写的 图像采集 显示程序。

; Worst-case tsu                                            ; N/A       ; None                             ; 7.927 ns                         ; fodd                                                 ; clk_syn:inst1|fodd_syn                               ; --                                         ; fpgaclk                                    ; 0            ;
; Worst-case tco                                            ; N/A       ; None                             ; 10.827 ns                        ; writefifo1:writefifo11|fifo1wrst_reg                 ; fifo1wrst                                            ; fpgaclk                                    ; --                                         ; 0            ;
; Worst-case tpd                                            ; N/A       ; None                             ; 18.751 ns                        ; dspaddr[5]                                           ; fifo1oe                                              ; --                                         ; --                                         ; 0            ;
; Worst-case th                                             ; N/A       ; None                             ; -0.525 ns                        ; dspaddr[12]                                          ; readfifo1:readfifo11|fifo1re_cnt[0]                  ; --                                         ; dspre                                      ; 0            ;
; Clock Setup: 'dspre'                                      ; 9.204 ns  ; 60.00 MHz ( period = 16.666 ns ) ; 134.01 MHz ( period = 7.462 ns ) ; readfifo1:readfifo11|fifo1re_cnt[7]                  ; readfifo1:readfifo11|fifo1re_cnt[7]                  ; dspre                                      ; dspre                                      ; 0            ;
; Clock Setup: 'altpll0:inst|altpll:altpll_component|_clk0' ; 10.194 ns ; 60.00 MHz ( period = 16.666 ns ) ; N/A                              ; clk_syn:inst1|hsyn_syn                               ; writefifo1:writefifo11|hsyn_pre                      ; altpll0:inst|altpll:altpll_component|_clk0 ; altpll0:inst|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'altpll0:inst|altpll:altpll_component|_clk0'  ; 0.499 ns  ; 60.00 MHz ( period = 16.666 ns ) ; N/A                              ; writefifo1:writefifo11|writefifo1_state.WRITE_UPPART ; writefifo1:writefifo11|writefifo1_state.WRITE_UPPART ; altpll0:inst|altpll:altpll_component|_clk0 ; altpll0:inst|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'dspre'                                       ; 0.499 ns  ; 60.00 MHz ( period = 16.666 ns ) ; N/A                              ; readfifo1:readfifo11|upperframe_readed               ; readfifo1:readfifo11|upperframe_readed               ; dspre                                      ; dspre                                      ; 0            ;
; Total number of failed paths                              ;           ;                                  ;                                  ;                                                      ;                                                      ;                                            ;                                            ; 0            ;
+-----------------------------------------------------------+-----------+----------------------------------+----------------------------------+------------------------------------------------------+------------------------------------------------------+--------------------------------------------+--------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C8Q208C8        ;      ;    ;             ;
; Timing Models                                         ; Preliminary        ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; fmax Requirement                                      ; 60 MHz             ;      ;    ;             ;
; Ignore Clock Settings                                 ; On                 ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                             ;
+--------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                            ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+--------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; altpll0:inst|altpll:altpll_component|_clk0 ;                    ; PLL output ; 60.0 MHz         ; 0.000 ns      ; 0.000 ns     ; fpgaclk  ; 2                     ; 1                   ; -2.290 ns ;              ;
; fpgaclk                                    ;                    ; User Pin   ; 30.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; dspre                                      ;                    ; User Pin   ; 60.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+--------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+