newboardconfig.fit.eqn

cyclone II 208c8编写的 图像采集 显示程序。

--dspaddr[6] is dspaddr[6] at PIN_182
--operation mode is input

dspaddr[6] = INPUT();


--dspaddr[9] is dspaddr[9] at PIN_180
--operation mode is input

dspaddr[9] = INPUT();


--dspaddr[10] is dspaddr[10] at PIN_191
--operation mode is input

dspaddr[10] = INPUT();


--dspaddr[8] is dspaddr[8] at PIN_170
--operation mode is input

dspaddr[8] = INPUT();


--dspaddr[13] is dspaddr[13] at PIN_189
--operation mode is input

dspaddr[13] = INPUT();


--dspaddr[12] is dspaddr[12] at PIN_181
--operation mode is input

dspaddr[12] = INPUT();


--dspaddr[7] is dspaddr[7] at PIN_192
--operation mode is input

dspaddr[7] = INPUT();


--dspaddr[11] is dspaddr[11] at PIN_171
--operation mode is input

dspaddr[11] = INPUT();


--dspaddr[3] is dspaddr[3] at PIN_185
--operation mode is input

dspaddr[3] = INPUT();


--dspaddr[4] is dspaddr[4] at PIN_193
--operation mode is input

dspaddr[4] = INPUT();


--dspaddr[5] is dspaddr[5] at PIN_169
--operation mode is input

dspaddr[5] = INPUT();


--dspaddr[2] is dspaddr[2] at PIN_168
--operation mode is input

dspaddr[2] = INPUT();


--dspoe is dspoe at PIN_208
--operation mode is input

dspoe = INPUT();


--dspaddr[1] is dspaddr[1] at PIN_195
--operation mode is input

dspaddr[1] = INPUT();


--dspre is dspre at PIN_3
--operation mode is input

dspre = INPUT();


--pclk is pclk at PIN_24
--operation mode is input

pclk = INPUT();


--fpgaclk is fpgaclk at PIN_27
--operation mode is input

fpgaclk = INPUT();


--fodd is fodd at PIN_30
--operation mode is input

fodd = INPUT();


--href is href at PIN_28
--operation mode is input

href = INPUT();


--hsyn is hsyn at PIN_39
--operation mode is input

hsyn = INPUT();


--vsyn is vsyn at PIN_31
--operation mode is input

vsyn = INPUT();


--R8019en is R8019en at PIN_152
--operation mode is output

R8019en = OUTPUT(!B1_R8019en);


--dspready is dspready at PIN_206
--operation mode is output

dspready = OUTPUT(VCC);


--fifo1we is fifo1we at PIN_105
--operation mode is output

fifo1we = OUTPUT(H1_fifo1we_reg);


--fifo1wrst is fifo1wrst at PIN_108
--operation mode is output

fifo1wrst = OUTPUT(H1_fifo1wrst_reg);


--cmosreset is cmosreset at PIN_35
--operation mode is output

cmosreset = OUTPUT(!K1_rst_cnt[17]);


--pwdn is pwdn at PIN_33
--operation mode is output

pwdn = OUTPUT(GND);


--fifo1re is fifo1re at PIN_106
--operation mode is output

fifo1re = OUTPUT(!B1L7);


--fifo1oe is fifo1oe at PIN_107
--operation mode is output

fifo1oe = OUTPUT(F1_fifo1oe);


--fifo1rrst is fifo1rrst at PIN_110
--operation mode is output

fifo1rrst = OUTPUT(!B1L8);


--fifo1rclk is fifo1rclk at PIN_113
--operation mode is output

fifo1rclk = OUTPUT(dspre);


--fifo1wclk is fifo1wclk at PIN_112
--operation mode is output

fifo1wclk = OUTPUT(D1_pclk_syn1);


--blank is blank at PIN_82
--operation mode is output

blank = OUTPUT(GND);


--vga_clk is vga_clk at PIN_67
--operation mode is output

vga_clk = OUTPUT(GND);


--vga_hsyn is vga_hsyn at PIN_70
--operation mode is output

vga_hsyn = OUTPUT(GND);


--fifo1data[7] is fifo1data[7] at PIN_104
--operation mode is output

fifo1data[7] = OUTPUT(H1_fifo1data[7]);


--fifo1data[6] is fifo1data[6] at PIN_103
--operation mode is output

fifo1data[6] = OUTPUT(H1_fifo1data[6]);


--fifo1data[5] is fifo1data[5] at PIN_102
--operation mode is output

fifo1data[5] = OUTPUT(H1_fifo1data[5]);


--fifo1data[4] is fifo1data[4] at PIN_101
--operation mode is output

fifo1data[4] = OUTPUT(H1_fifo1data[4]);


--fifo1data[3] is fifo1data[3] at PIN_99
--operation mode is output

fifo1data[3] = OUTPUT(H1_fifo1data[3]);


--fifo1data[2] is fifo1data[2] at PIN_97
--operation mode is output

fifo1data[2] = OUTPUT(H1_fifo1data[2]);


--fifo1data[1] is fifo1data[1] at PIN_96
--operation mode is output

fifo1data[1] = OUTPUT(H1_fifo1data[1]);


--fifo1data[0] is fifo1data[0] at PIN_95
--operation mode is output

fifo1data[0] = OUTPUT(H1_fifo1data[0]);


--fifo1s[2] is fifo1s[2] at PIN_116
--operation mode is output

fifo1s[2] = OUTPUT(OPNDRN(VCC));


--fifo1s[1] is fifo1s[1] at PIN_115
--operation mode is output

fifo1s[1] = OUTPUT(OPNDRN(VCC));


--fifo1s[0] is fifo1s[0] at PIN_114
--operation mode is output

fifo1s[0] = OUTPUT(OPNDRN(VCC));


--fifo2s[2] is fifo2s[2] at PIN_144
--operation mode is output

fifo2s[2] = OUTPUT(OPNDRN(VCC));


--fifo2s[1] is fifo2s[1] at PIN_143
--operation mode is output

fifo2s[1] = OUTPUT(OPNDRN(VCC));


--fifo2s[0] is fifo2s[0] at PIN_142
--operation mode is output

fifo2s[0] = OUTPUT(OPNDRN(VCC));


--flashaddr[19] is flashaddr[19] at PIN_147
--operation mode is output

flashaddr[19] = OUTPUT(GND);


--flashaddr[18] is flashaddr[18] at PIN_146
--operation mode is output

flashaddr[18] = OUTPUT(GND);


--flashaddr[17] is flashaddr[17] at PIN_145
--operation mode is output

flashaddr[17] = OUTPUT(GND);


--flashaddr[16] is flashaddr[16] at PIN_151
--operation mode is output

flashaddr[16] = OUTPUT(GND);


--flashaddr[15] is flashaddr[15] at PIN_150
--operation mode is output

flashaddr[15] = OUTPUT(GND);


--flashaddr[14] is flashaddr[14] at PIN_149
--operation mode is output

flashaddr[14] = OUTPUT(GND);


--uv[7] is uv[7] at PIN_64
--operation mode is bidir

uv[7] = BIDIR(OPNDRN(K1_rst_cnt[17]));


--uv[6] is uv[6] at PIN_61
--operation mode is bidir

uv[6] = BIDIR(OPNDRN(K1_rst_cnt[17]));


--uv[5] is uv[5] at PIN_63
--operation mode is bidir

uv[5] = BIDIR(OPNDRN(K1_rst_cnt[17]));


--uv[4] is uv[4] at PIN_59
--operation mode is bidir

uv[4] = BIDIR(OPNDRN(K1_rst_cnt[17]));


--uv[3] is uv[3] at PIN_60
--operation mode is bidir

uv[3] = BIDIR(OPNDRN(K1_rst_cnt[17]));


--uv[2] is uv[2] at PIN_57
--operation mode is bidir

uv[2] = BIDIR(OPNDRN(K1_rst_cnt[17]));


--uv[1] is uv[1] at PIN_58
--operation mode is bidir

uv[1] = BIDIR(OPNDRN(K1_rst_cnt[17]));


--uv[0] is uv[0] at PIN_56
--operation mode is bidir

uv[0] = BIDIR(OPNDRN(K1_rst_cnt[17]));


--H1_fifo1data[7] is writefifo1:writefifo11|fifo1data[7] at PIN_48
--operation mode is bidir

H1_fifo1data[7] = y[7];

--y[7] is y[7] at PIN_48
--operation mode is bidir

y[7] = BIDIR(OPNDRN(K1_rst_cnt[17]));


--H1_fifo1data[6] is writefifo1:writefifo11|fifo1data[6] at PIN_46
--operation mode is bidir

H1_fifo1data[6] = y[6];

--y[6] is y[6] at PIN_46
--operation mode is bidir

y[6] = BIDIR(OPNDRN(K1_rst_cnt[17]));


--H1_fifo1data[5] is writefifo1:writefifo11|fifo1data[5] at PIN_47
--operation mode is bidir

H1_fifo1data[5] = y[5];

--y[5] is y[5] at PIN_47
--operation mode is bidir

y[5] = BIDIR(OPNDRN(K1_rst_cnt[17]));


--H1_fifo1data[4] is writefifo1:writefifo11|fifo1data[4] at PIN_44
--operation mode is bidir

H1_fifo1data[4] = y[4];

--y[4] is y[4] at PIN_44
--operation mode is bidir

y[4] = BIDIR(OPNDRN(K1_rst_cnt[17]));


--H1_fifo1data[3] is writefifo1:writefifo11|fifo1data[3] at PIN_45
--operation mode is bidir

H1_fifo1data[3] = y[3];

--y[3] is y[3] at PIN_45
--operation mode is bidir

y[3] = BIDIR(OPNDRN(K1_rst_cnt[17]));


--H1_fifo1data[2] is writefifo1:writefifo11|fifo1data[2] at PIN_41
--operation mode is bidir

H1_fifo1data[2] = y[2];

--y[2] is y[2] at PIN_41
--operation mode is bidir

y[2] = BIDIR(OPNDRN(K1_rst_cnt[17]));


--H1_fifo1data[1] is writefifo1:writefifo11|fifo1data[1] at PIN_43
--operation mode is bidir

H1_fifo1data[1] = y[1];

--y[1] is y[1] at PIN_43
--operation mode is bidir

y[1] = BIDIR(OPNDRN(K1_rst_cnt[17]));


--H1_fifo1data[0] is writefifo1:writefifo11|fifo1data[0] at PIN_40
--operation mode is bidir

H1_fifo1data[0] = y[0];

--y[0] is y[0] at PIN_40
--operation mode is bidir

y[0] = BIDIR(OPNDRN(K1_rst_cnt[17]));




--B1L6 is dsp:dsp1|cmosrstport~55clkctrl at CLKCTRL_G5
B1L6 = cycloneii_clkctrl(.INCLK[0] = B1L5) WITH (clock_type = "Global Clock");


--J1L2 is altpll0:inst|altpll:altpll_component|_clk0~clkctrl at CLKCTRL_G3
J1L2 = cycloneii_clkctrl(.INCLK[0] = J1__clk0) WITH (clock_type = "Global Clock");


--D1L8 is clk_syn:inst1|pclk_syn1~clkctrl at CLKCTRL_G7
D1L8 = cycloneii_clkctrl(.INCLK[0] = D1_pclk_syn1) WITH (clock_type = "Global Clock");


--B1L10 is dsp:dsp1|fifo1wrrstport~4clkctrl at CLKCTRL_G6
B1L10 = cycloneii_clkctrl(.INCLK[0] = B1L9) WITH (clock_type = "Global Clock");


--D1L9 is clk_syn:inst1|pclk_syn1~feeder at LCCOMB_X16_Y10_N8
D1L9 = pclk;


--H1L29 is writefifo1:writefifo11|fodd_pre~feeder at LCCOMB_X19_Y14_N6
H1L29 = D1_fodd_syn;


--D1L2 is clk_syn:inst1|fodd_syn~feeder at LCCOMB_X19_Y14_N10
D1L2 = fodd;


--D1L11 is clk_syn:inst1|vsyn_syn~feeder at LCCOMB_X19_Y8_N30
D1L11 = href;


--H1L99 is writefifo1:writefifo11|vsyn_pre~feeder at LCCOMB_X18_Y8_N0
H1L99 = D1_href_syn;


--D1L6 is clk_syn:inst1|hsyn_syn~feeder at LCCOMB_X19_Y7_N4
D1L6 = hsyn;


--D1L4 is clk_syn:inst1|href_syn~feeder at LCCOMB_X18_Y8_N2
D1L4 = vsyn;


--H1L102 is writefifo1:writefifo11|writefifo1_state.WRITE_INIT0~feeder at LCCOMB_X19_Y15_N0
H1L102 = VCC;