newboardconfig.fit.rpt

cyclone II 208c8编写的 图像采集 显示程序。

; SignalProbe signals routed during normal compilation ; Off                            ; Off                            ;
; Router Timing Optimization Level                     ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                          ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                             ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                                 ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                          ; Off                            ; Off                            ;
; PowerPlay Power Optimization                         ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                      ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing           ; On                             ; On                             ;
; Limit to One Fitting Attempt                         ; Off                            ; Off                            ;
; Final Placement Optimizations                        ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations          ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                        ; 1                              ; 1                              ;
; PCI I/O                                              ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                            ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                   ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/Cyclone II       ; Auto                           ; Auto                           ;
; Auto Delay Chains                                    ; On                             ; On                             ;
; Auto Merge PLLs                                      ; On                             ; On                             ;
; Fitter Effort                                        ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                      ; Normal                         ; Normal                         ;
; Auto Global Clock                                    ; On                             ; On                             ;
; Auto Global Register Control Signals                 ; On                             ; On                             ;
+------------------------------------------------------+--------------------------------+--------------------------------+


+-------------------------------------------------------------------------+
; Fitter Device Options                                                   ;
+----------------------------------------------+--------------------------+
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Active Serial            ;
; Error detection CRC                          ; Off                      ;
; Reserve ASDO pin after configuration.        ; As input tri-stated      ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in F:/newboardconfig9/newboardconfig.fit.eqn.


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in F:/newboardconfig9/newboardconfig.pin.


+-----------------------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                                                       ;
+---------------------------------------------+-------------------------------------------------------+
; Resource                                    ; Usage                                                 ;
+---------------------------------------------+-------------------------------------------------------+
; Total logic elements                        ; 102 / 8,256 ( 1 % )                                   ;
;     -- Combinational with no register       ; 24                                                    ;
;     -- Register only                        ; 8                                                     ;
;     -- Combinational with a register        ; 70                                                    ;
;                                             ;                                                       ;
; Logic element usage by number of LUT inputs ;                                                       ;
;     -- 4 input functions                    ; 20                                                    ;
;     -- 3 input functions                    ; 10                                                    ;
;     -- <=2 input functions                  ; 64                                                    ;
;     -- Register only                        ; 8                                                     ;
;         -- Combinational cells for routing  ; 7                                                     ;
;                                             ;                                                       ;
; Logic elements by mode                      ;                                                       ;
;     -- normal mode                          ; 41                                                    ;
;     -- arithmetic mode                      ; 53                                                    ;
;                                             ;                                                       ;
; Total registers                             ; 78 / 8,256 ( < 1 % )                                  ;
; Total LABs                                  ; 12 / 516 ( 2 % )                                      ;
; User inserted logic elements                ; 0                                                     ;
; Virtual pins                                ; 0                                                     ;
; I/O pins                                    ; 101 / 138 ( 73 % )                                    ;
;     -- Clock pins                           ; 2 / 4 ( 50 % )                                        ;
; Global signals                              ; 4                                                     ;
; M4Ks                                        ; 0 / 36 ( 0 % )                                        ;