__projnav.log

多功能数字时钟设计的源程序,可以实现计时闹钟鸣笛等基本功能.

Constraints file: seg7.pcf.
Loading device for application Rf_Device from file '3s400.nph' in environment
C:/Xilinx.
   "seg7" is an NCD, version 3.1, device xc3s400, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.35 2005-01-22".


Device Utilization Summary:

   Number of BUFGMUXs                  1 out of 8      12%
   Number of External IOBs            16 out of 173     9%
      Number of LOCed IOBs            16 out of 16    100%

   Number of Slices                   64 out of 3584    1%
      Number of SLICEMs                0 out of 1792    0%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

WARNING:Par:276 - The signal stop_IBUF has no load
WARNING:Par:276 - The signal start_IBUF has no load

Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98977b) REAL time: 2 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.8
.
Phase 4.8 (Checksum:9929eb) REAL time: 2 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 2 secs 

Phase 6.18
Phase 6.18 (Checksum:39386fa) REAL time: 2 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 2 secs 

Writing design to file seg7.ncd


Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 

Starting Router

Phase 1: 414 unrouted;       REAL time: 2 secs 

Phase 2: 392 unrouted;       REAL time: 2 secs 

Phase 3: 132 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 


WARNING:CLK Net:count<19>
may have excessive skew because 8 CLK pins and 2 NON_CLK pins
failed to route using a CLK template.

Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 1 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP |      BUFGMUX0| No   |   21 |  0.020     |  1.034      |
+---------------------+--------------+------+------+------------+-------------+
|           count<19> |         Local|      |   10 |  1.347     |  2.868      |
+---------------------+--------------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 3 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  77 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 2
Number of info messages: 1

Writing design to file seg7.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s400.nph' in environment
C:/Xilinx.
   "seg7" is an NCD, version 3.1, device xc3s400, package ft256, speed -4

Analysis completed Fri Jan 19 05:41:01 2007
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 2 secs 







Started process "Generate Programming File".

WARNING:PhysDesignRules:367 - The signal <stop_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <start_IBUF> is incomplete. The signal
   does not drive any load pins in the design.


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "/../seg7/segt.v"
Module <seg7> compiled
No errors in compilation
Analysis of file <"seg7.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <seg7>.
WARNING:Xst:905 - "/../seg7/segt.v" line 188: The signals <sec_seg1, sec_seg2, sec_seg3, sec_seg4> are missing in the sensitivity list of always block.
Module <seg7> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <seg7>.
    Related source file is "/../seg7/segt.v".
WARNING:Xst:647 - Input <stop> is never used.
WARNING:Xst:647 - Input <start> is never used.
    Found 16x8-bit ROM for signal <sec_seg1>.
    Found 16x8-bit ROM for signal <sec_seg2>.
    Found 16x8-bit ROM for signal <sec_seg3>.
    Found 1-of-4 decoder for signal <an>.
    Found 8-bit 4-to-1 multiplexer for signal <seg>.
    Found 20-bit up counter for signal <count>.
    Found 19-bit up counter for signal <scan>.
    Found 4-bit up counter for signal <sec_count1>.
    Found 4-bit up counter for signal <sec_count2>.
    Found 4-bit up counter for signal <sec_count3>.
    Found 3-bit up counter for signal <sec_count4>.
    Summary:
	inferred   3 ROM(s).
	inferred   6 Counter(s).
	inferred   8 Multiplexer(s).
	inferred   1 Decoder(s).
Unit <seg7> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 3
 16x8-bit ROM                      : 3
# Counters                         : 6
 19-bit up counter                 : 1
 20-bit up counter                 : 1
 3-bit up counter                  : 1
 4-bit up counter                  : 3
# Multiplexers                     : 1
 8-bit 4-to-1 multiplexer          : 1
# Decoders                         : 1
 1-of-4 decoder                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <seg7> ...
Loading device for application Rf_Device from file '3s400.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block seg7, actual ratio is 1.
FlipFlop scan_17 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400ft256-4 

 Number of Slices:                      62  out of   3584     1%  
 Number of Slice Flip Flops:            55  out of   7168     0%  
 Number of 4 input LUTs:               113  out of   7168     1%  
 Number of bonded IOBs:                 16  out of    173     9%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 40    |
count_19:Q                         | NONE                   | 15    |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 7.558ns (Maximum Frequency: 132.310MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 11.106ns
   Maximum combinational path delay: No path found

=========================================================================


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\wqs/_ngo -uc seg7.ucf -p
xc3s400-ft256-4 seg7.ngc seg7.ngd 

Reading NGO file 'D:/WQS/seg7.ngc' ...

Applying constraints in "seg7.ucf" to the design...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "seg7.ngd" ...

Writing NGDBUILD log file "seg7.bld"...

NGDBUILD done.




Started process "Map".

Using target part "3s400ft256-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    4
Logic Utilization:
  Number of Slice Flip Flops:          55 out of   7,168    1%
  Number of 4 input LUTs:              77 out of   7,168    1%
Logic Distribution:
  Number of occupied Slices:                           64 out of   3,584    1%
    Number of Slices containing only related logic:      64 out of      64  100%
    Number of Slices containing unrelated logic:          0 out of      64    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:            115 out of   7,168    1%
  Number used as logic:                 77
  Number used as a route-thru:          38
  Number of bonded IOBs:               16 out of     173    9%
  Number of GCLKs:                     1 out of       8   12%

Total equivalent gate count for design:  1,151
Additional JTAG gate count for IOBs:  768
Peak Memory Usage:  109 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "seg7_map.mrp" for details.




Started process "Place & Route".




Constraints file: seg7.pcf.
Loading device for application Rf_Device from file '3s400.nph' in environment
C:/Xilinx.
   "seg7" is an NCD, version 3.1, device xc3s400, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.35 2005-01-22".


Device Utilization Summary:

   Number of BUFGMUXs                  1 out of 8      12%
   Number of External IOBs            16 out of 173     9%
      Number of LOCed IOBs            16 out of 16    100%

   Number of Slices                   64 out of 3584    1%
      Number of SLICEMs                0 out of 1792    0%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

WARNING:Par:276 - The signal stop_IBUF has no load
WARNING:Par:276 - The signal start_IBUF has no load

Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98977b) REAL time: 2 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.2
.