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Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "/../seg7/segt.v"Module <seg7> compiledNo errors in compilationAnalysis of file <"seg7.prj"> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <seg7>.WARNING:Xst:905 - "/../seg7/segt.v" line 183: The signals <sec_seg1, sec_seg2, sec_seg3, sec_seg4> are missing in the sensitivity list of always block.Module <seg7> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <seg7>. Related source file is "/../seg7/segt.v".WARNING:Xst:647 - Input <stop> is never used.WARNING:Xst:647 - Input <start> is never used. Found 16x8-bit ROM for signal <sec_seg1>. Found 16x8-bit ROM for signal <sec_seg2>. Found 16x8-bit ROM for signal <sec_seg3>. Found 1-of-4 decoder for signal <an>. Found 8-bit 4-to-1 multiplexer for signal <seg>. Found 20-bit up counter for signal <count>. Found 19-bit up counter for signal <scan>. Found 4-bit up counter for signal <sec_count1>. Found 4-bit up counter for signal <sec_count2>. Found 4-bit up counter for signal <sec_count3>. Found 3-bit up counter for signal <sec_count4>. Summary: inferred 3 ROM(s). inferred 6 Counter(s). inferred 8 Multiplexer(s). inferred 1 Decoder(s).Unit <seg7> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# ROMs : 3 16x8-bit ROM : 3# Counters : 6 19-bit up counter : 1 20-bit up counter : 1 3-bit up counter : 1 4-bit up counter : 3# Multiplexers : 1 8-bit 4-to-1 multiplexer : 1# Decoders : 1 1-of-4 decoder : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <seg7> ...Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block seg7, actual ratio is 3.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 3s200ft256-4 Number of Slices: 58 out of 1920 3% Number of Slice Flip Flops: 54 out of 3840 1% Number of 4 input LUTs: 105 out of 3840 2% Number of bonded IOBs: 16 out of 173 9% Number of GCLKs: 1 out of 8 12% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk | BUFGP | 39 |count_19:Q | NONE | 15 |-----------------------------------+------------------------+-------+INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.Timing Summary:---------------Speed Grade: -4 Minimum period: 7.716ns (Maximum Frequency: 129.601MHz) Minimum input arrival time before clock: No path found Maximum output required time after clock: 11.106ns Maximum combinational path delay: No path found=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "/../seg7/segt.v"ERROR:HDLCompilers:28 - "/../seg7/segt.v" line 177 'CLK' has not been declaredModule <seg7> compiledAnalysis of file <"seg7.prj"> failed.--> Total memory usage is 76800 kilobytesNumber of errors : 1 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "/../seg7/segt.v"Module <seg7> compiledNo errors in compilationAnalysis of file <"seg7.prj"> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <seg7>.WARNING:Xst:905 - "/../seg7/segt.v" line 188: The signals <sec_seg1, sec_seg2, sec_seg3, sec_seg4> are missing in the sensitivity list of always block.Module <seg7> is correct for synthesis. Set property "resynthesize = true" for unit <seg7>.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <seg7>. Related source file is "/../seg7/segt.v".WARNING:Xst:647 - Input <stop> is never used.WARNING:Xst:647 - Input <start> is never used. Found 16x8-bit ROM for signal <sec_seg1>. Found 16x8-bit ROM for signal <sec_seg2>. Found 16x8-bit ROM for signal <sec_seg3>. Found 1-of-4 decoder for signal <an>. Found 8-bit 4-to-1 multiplexer for signal <seg>. Found 20-bit up counter for signal <count>. Found 19-bit up counter for signal <scan>. Found 4-bit up counter for signal <sec_count1>. Found 4-bit up counter for signal <sec_count2>. Found 4-bit up counter for signal <sec_count3>. Found 3-bit up counter for signal <sec_count4>. Summary: inferred 3 ROM(s). inferred 6 Counter(s). inferred 8 Multiplexer(s). inferred 1 Decoder(s).Unit <seg7> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# ROMs : 3 16x8-bit ROM : 3# Counters : 6 19-bit up counter : 1 20-bit up counter : 1 3-bit up counter : 1 4-bit up counter : 3# Multiplexers : 1 8-bit 4-to-1 multiplexer : 1# Decoders : 1 1-of-4 decoder : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <seg7> ...Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block seg7, actual ratio is 3.FlipFlop scan_17 has been replicated 1 time(s)=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 3s200ft256-4 Number of Slices: 62 out of 1920 3% Number of Slice Flip Flops: 55 out of 3840 1% Number of 4 input LUTs: 113 out of 3840 2% Number of bonded IOBs: 16 out of 173 9% Number of GCLKs: 1 out of 8 12% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk | BUFGP | 40 |count_19:Q | NONE | 15 |-----------------------------------+------------------------+-------+INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.Timing Summary:---------------Speed Grade: -4 Minimum period: 7.558ns (Maximum Frequency: 132.310MHz) Minimum input arrival time before clock: No path found Maximum output required time after clock: 11.106ns Maximum combinational path delay: No path found=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd d:\wqs/_ngo -uc seg7.ucf -pxc3s200-ft256-4 seg7.ngc seg7.ngd Reading NGO file 'D:/WQS/seg7.ngc' ...Applying constraints in "seg7.ucf" to the design...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "seg7.ngd" ...Writing NGDBUILD log file "seg7.bld"...NGDBUILD done.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd d:\wqs/_ngo -uc seg7.ucf -pxc3s200-ft256-4 seg7.ngc seg7.ngd Reading NGO file 'D:/WQS/seg7.ngc' ...Applying constraints in "seg7.ucf" to the design...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "seg7.ngd" ...Writing NGDBUILD log file "seg7.bld"...NGDBUILD done.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd d:\wqs/_ngo -uc seg7.ucf -pxc3s200-ft256-4 seg7.ngc seg7.ngd Reading NGO file 'D:/WQS/seg7.ngc' ...Applying constraints in "seg7.ucf" to the design...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "seg7.ngd" ...Writing NGDBUILD log file "seg7.bld"...NGDBUILD done.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Map".Using target part "3s200ft256-4".Mapping design into LUTs...Running directed packing...Running delay-based LUT packing...Running related packing...Design Summary:Number of errors: 0Number of warnings: 4Logic Utilization:⌨️ 快捷键说明
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