seg7.syr

多功能数字时钟设计的源程序,可以实现计时闹钟鸣笛等基本功能.

Release 7.1i - xst H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Reading design: seg7.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "seg7.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "seg7"
Output Format                      : NGC
Target Device                      : xc3s400-4-ft256

---- Source Options
Top Module Name                    : seg7
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : seg7.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "segt.v"
Module <seg7> compiled
No errors in compilation
Analysis of file <"seg7.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <seg7>.
Module <seg7> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <seg7>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <seg7>.
    Related source file is "segt.v".
    Found 16x8-bit ROM for signal <sec_seg1>.
    Found 16x8-bit ROM for signal <sec_seg2>.
    Found 16x8-bit ROM for signal <sec_seg3>.
    Found 1-of-4 decoder for signal <an>.
    Found 8-bit 4-to-1 multiplexer for signal <seg>.
    Found 20-bit up counter for signal <count>.
    Found 19-bit up counter for signal <scan>.
    Found 4-bit up counter for signal <sec_count1>.
    Found 4-bit up counter for signal <sec_count2>.
    Found 4-bit up counter for signal <sec_count3>.
    Found 3-bit up counter for signal <sec_count4>.
    Found 1-bit register for signal <x>.
    Summary:
	inferred   3 ROM(s).
	inferred   6 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   8 Multiplexer(s).
	inferred   1 Decoder(s).
Unit <seg7> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 3
 16x8-bit ROM                      : 3
# Counters                         : 6
 19-bit up counter                 : 1
 20-bit up counter                 : 1
 3-bit up counter                  : 1
 4-bit up counter                  : 3
# Registers                        : 1
 1-bit register                    : 1
# Multiplexers                     : 1
 8-bit 4-to-1 multiplexer          : 1
# Decoders                         : 1
 1-of-4 decoder                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <seg7> ...
Loading device for application Rf_Device from file '3s400.nph' in environment E:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block seg7, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : seg7.ngr
Top Level Output File Name         : seg7
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 16

Macro Statistics :
# ROMs                             : 3
#      16x8-bit ROM                : 3
# Registers                        : 7
#      1-bit register              : 1
#      20-bit register             : 6
# Multiplexers                     : 1
#      8-bit 4-to-1 multiplexer    : 1
# Decoders                         : 1
#      1-of-4 decoder              : 1
# Adders/Subtractors               : 6
#      20-bit adder                : 6

Cell Usage :
# BELS                             : 205
#      GND                         : 1
#      INV                         : 6
#      LUT1                        : 20
#      LUT1_L                      : 18
#      LUT2                        : 7
#      LUT3                        : 22
#      LUT3_L                      : 1
#      LUT4                        : 42
#      LUT4_D                      : 3
#      LUT4_L                      : 2
#      MUXCY                       : 37
#      MUXF5                       : 8
#      VCC                         : 1
#      XORCY                       : 37
# FlipFlops/Latches                : 55
#      FDCE                        : 15
#      FDP                         : 1
#      FDR                         : 39
# Clock Buffers                    : 2
#      BUFGP                       : 2
# IO Buffers                       : 14
#      IBUF                        : 2
#      OBUF                        : 12
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400ft256-4 

 Number of Slices:                      64  out of   3584     1%  
 Number of Slice Flip Flops:            55  out of   7168     0%  
 Number of 4 input LUTs:               115  out of   7168     1%  
 Number of bonded IOBs:                 16  out of    173     9%  
 Number of GCLKs:                        2  out of      8    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 39    |
stop                               | BUFGP                  | 1     |
count_19:Q                         | NONE                   | 15    |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 7.558ns (Maximum Frequency: 132.310MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 11.132ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 7.558ns (frequency: 132.310MHz)
  Total number of paths / destination ports: 1161 / 78
-------------------------------------------------------------------------
Delay:               7.558ns (Levels of Logic = 3)
  Source:            count_19 (FF)
  Destination:       count_18 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: count_19 to count_18
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             17   0.720   1.371  count_19 (count_19)
     LUT4:I3->O            1   0.551   0.827  _n000016 (CHOICE180)
     LUT4_D:I3->O          1   0.551   0.827  _n000020 (CHOICE181)
     LUT4:I3->O           10   0.551   1.134  _n000093_1 (_n000093)
     FDR:R                     1.026          count_18
    ----------------------------------------
    Total                      7.558ns (3.399ns logic, 4.159ns route)
                                       (45.0% logic, 55.0% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'count_19:Q'
  Clock period: 5.836ns (frequency: 171.350MHz)
  Total number of paths / destination ports: 127 / 26
-------------------------------------------------------------------------
Delay:               5.836ns (Levels of Logic = 2)
  Source:            sec_count1_2 (FF)
  Destination:       sec_count4_2 (FF)
  Source Clock:      count_19:Q rising
  Destination Clock: count_19:Q rising

  Data Path: sec_count1_2 to sec_count4_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            13   0.720   1.509  sec_count1_2 (sec_count1_2)
     LUT4:I0->O            1   0.551   0.996  Ker024_SW0 (N133)
     LUT4:I1->O            3   0.551   0.907  _n0025 (_n0025)
     FDCE:CE                   0.602          sec_count4_0
    ----------------------------------------
    Total                      5.836ns (2.424ns logic, 3.412ns route)
                                       (41.5% logic, 58.5% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 31 / 12
-------------------------------------------------------------------------
Offset:              9.930ns (Levels of Logic = 3)
  Source:            scan_17 (FF)
  Destination:       seg<7> (PAD)
  Source Clock:      clk rising

  Data Path: scan_17 to seg<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             21   0.720   1.854  scan_17 (scan_17)
     LUT3:I0->O            1   0.551   0.000  scan<17>14 (MUX_BLOCK_N16)
     MUXF5:I1->O           1   0.360   0.801  Mmux_seg_seg<0>_seg<0>_rn_5 (seg_7_OBUF)
     OBUF:I->O                 5.644          seg_7_OBUF (seg<7>)
    ----------------------------------------
    Total                      9.930ns (7.275ns logic, 2.655ns route)
                                       (73.3% logic, 26.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'count_19:Q'
  Total number of paths / destination ports: 103 / 7
-------------------------------------------------------------------------
Offset:              11.132ns (Levels of Logic = 4)
  Source:            sec_count1_1 (FF)
  Destination:       seg<7> (PAD)
  Source Clock:      count_19:Q rising

  Data Path: sec_count1_1 to seg<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            13   0.720   1.509  sec_count1_1 (sec_count1_1)
     LUT4:I0->O            1   0.551   0.996  Mrom_sec_seg1_inst_lut4_231 (sec_seg1<7>)
     LUT3:I1->O            1   0.551   0.000  scan<17>15 (MUX_BLOCK_N17)
     MUXF5:I0->O           1   0.360   0.801  Mmux_seg_seg<0>_seg<0>_rn_5 (seg_7_OBUF)
     OBUF:I->O                 5.644          seg_7_OBUF (seg<7>)
    ----------------------------------------
    Total                     11.132ns (7.826ns logic, 3.306ns route)
                                       (70.3% logic, 29.7% route)

=========================================================================
CPU : 8.55 / 13.53 s | Elapsed : 9.00 / 12.00 s
 
--> 

Total memory usage is 101488 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    1 (   0 filtered)