seg7.par

多功能数字时钟设计的源程序,可以实现计时闹钟鸣笛等基本功能.

Release 7.1i par H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

IBM-D11992A0FB7::  Fri Jan 19 14:47:01 2007

par -w -intstyle ise -ol std -t 1 seg7_map.ncd seg7.ncd seg7.pcf 


Constraints file: seg7.pcf.
Loading device for application Rf_Device from file '3s400.nph' in environment
E:/Xilinx.
   "seg7" is an NCD, version 3.1, device xc3s400, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.35 2005-01-22".


Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 8      25%
   Number of External IOBs            16 out of 173     9%
      Number of LOCed IOBs            16 out of 16    100%

   Number of Slices                   65 out of 3584    1%
      Number of SLICEMs                0 out of 1792    0%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:989783) REAL time: 6 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 6 secs 

Phase 3.2
......
.......................


Phase 3.2 (Checksum:98b49a) REAL time: 6 secs 

Phase 4.8
.
Phase 4.8 (Checksum:993fb7) REAL time: 6 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 6 secs 

Phase 6.18
Phase 6.18 (Checksum:39386fa) REAL time: 6 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 6 secs 

Writing design to file seg7.ncd


Total REAL time to Placer completion: 6 secs 
Total CPU time to Placer completion: 1 secs 

Starting Router

Phase 1: 426 unrouted;       REAL time: 6 secs 

Phase 2: 404 unrouted;       REAL time: 7 secs 

Phase 3: 142 unrouted;       REAL time: 7 secs 

Phase 4: 0 unrouted;       REAL time: 7 secs 


WARNING:CLK Net:count<19>
may have excessive skew because 8 CLK pins and 2 NON_CLK pins
failed to route using a CLK template.

Total REAL time to Router completion: 7 secs 
Total CPU time to Router completion: 1 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP |      BUFGMUX0| No   |   20 |  0.020     |  1.034      |
+---------------------+--------------+------+------+------------+-------------+
|          stop_BUFGP |      BUFGMUX1| No   |    1 |  0.000     |  1.033      |
+---------------------+--------------+------+------+------------+-------------+
|           count<19> |         Local|      |   10 |  0.769     |  2.292      |
+---------------------+--------------+------+------+------------+-------------+

INFO:Par:340 - 
   The Delay report will not be generated when running non-timing driven PAR
   with effort level Standard or Medium. If a delay report is required please do
   one of the following:  1) use effort level High, 2) use the following
   environment variable "XIL_PAR_GENERATE_DLY_REPORT", 3) create Timing
   constraints for the design.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 7 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  77 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file seg7.ncd



PAR done!