segt.v

多功能数字时钟设计的源程序,可以实现计时闹钟鸣笛等基本功能.

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    09:15:28 12/02/05
// Design Name:    
// Module Name:    seg7
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module seg7(clk,start,stop,clr,an,seg);
    input clk;
	input start,stop,clr;
    output [3:0] an;
    output [7:0] seg;

	 reg [3:0] an;
	 reg [7:0] seg;

	 reg [19:0] count=20'b00000000000000000000;
	 reg [3:0] sec_count1,sec_count2,sec_count3;
	 reg [2:0] sec_count4;
	 reg [18:0]	scan;
	 reg [7:0] sec_seg1,sec_seg2,sec_seg3,sec_seg4;
	 
	 reg x;

	 wire second;
	 wire start;
	 wire stop;
	 wire clr;
	 wire [1:0] scan_clk;

	 

	 assign second = count[19];
	 assign scan_clk = scan[18:17];  

	always @(posedge clk )	 //秒信号提取
	begin
		if(count[19:0] == 20'b11110100001001000000 ) 					  
			count <=20'b00000000000000000000;
		else
			count <= count + 1;				
	end	  
	    
 always @ (posedge start or posedge stop)
  	  begin
	  if(start)
	    x=1'b1;
		 else   x=1'b0;
		 end

  always @(posedge second or posedge clr)	 //时钟计数
		begin
		  if(clr)
			begin				  //清零
				sec_count1 <=4'd0 ;
			   sec_count2 <=4'd0 ;
			   sec_count3 <=4'd0 ;
			   sec_count4 <=3'd0;
	       end
		else	   if(x==1'b1) 
			  	   begin
		   	   if(sec_count1 == 4'd9)
			         begin
				      sec_count1 <= 4'd0;				
			    	     if(sec_count2 == 4'd9)
				            begin
				   	      sec_count2 <= 4'd0;
					          if(sec_count3 == 4'd9)
					            begin
						         sec_count3 <= 4'd0;
						            if(sec_count4 == 3'd5)
							         sec_count4 <= 3'd0;
					     	         else
						   	       sec_count4 <= sec_count4 + 1;
					             end
					           else
						        sec_count3 <= sec_count3 + 1;
			   	          end
				         else
					      sec_count2 <= sec_count2 + 1;
			           end
			        else
				     sec_count1 <= sec_count1 + 1;							
			        end
			     /*else 
			      begin
	            sec_count1 <= sec_count1 ;
			      sec_count2 <= sec_count2 ;
			      sec_count3 <= sec_count3 ;
			      sec_count4 <= sec_count4 ;
			      end*/

	end 

	always @(sec_count1)	  //7段码译码器
	begin
		case(sec_count1)
			4'b0000:	sec_seg1 <= 8'b00000011; //0
			4'b0001:	sec_seg1 <= 8'b10011111; //1
			4'b0010:	sec_seg1 <= 8'b00100101; //2
			4'b0011:	sec_seg1 <= 8'b00001101; //3
			4'b0100:	sec_seg1 <= 8'b10011001; //4
			4'b0101:	sec_seg1 <= 8'b01001001; //5
			4'b0110:	sec_seg1 <= 8'b01000001; //6
			4'b0111:	sec_seg1 <= 8'b00011111; //7
			4'b1000:	sec_seg1 <= 8'b00000001; //8
			4'b1001:	sec_seg1 <= 8'b00001001; //9
		   default: sec_seg1 <= 8'b11111111; //black
		 endcase			
	end

	always @(sec_count2)
	begin
		case(sec_count2)
			4'b0000:	sec_seg2 <= 8'b00000011; //0
			4'b0001:	sec_seg2 <= 8'b10011111; //1
			4'b0010:	sec_seg2 <= 8'b00100101; //2
			4'b0011:	sec_seg2 <= 8'b00001101; //3
			4'b0100:	sec_seg2 <= 8'b10011001; //4
			4'b0101:	sec_seg2 <= 8'b01001001; //5
			4'b0110:	sec_seg2 <= 8'b01000001; //6
			4'b0111:	sec_seg2 <= 8'b00011111; //7
			4'b1000:	sec_seg2 <= 8'b00000001; //8
			4'b1001:	sec_seg2 <= 8'b00001001; //9
		   default: sec_seg2 <= 8'b11111111; //black
		 endcase			
	end

	always @(sec_count3)
	begin
		case(sec_count3)
			4'b0000:	sec_seg3 <= 8'b00000010; //0
			4'b0001:	sec_seg3 <= 8'b10011110; //1
			4'b0010:	sec_seg3 <= 8'b00100100; //2
			4'b0011:	sec_seg3 <= 8'b00001100; //3
			4'b0100:	sec_seg3 <= 8'b10011000; //4
			4'b0101:	sec_seg3 <= 8'b01001000; //5
			4'b0110:	sec_seg3 <= 8'b01000000; //6
			4'b0111:	sec_seg3 <= 8'b00011110; //7
			4'b1000:	sec_seg3 <= 8'b00000000; //8
			4'b1001:	sec_seg3 <= 8'b00001000; //9
		   default: sec_seg3 <= 8'b11111110; //black
		 endcase			
	end

	always @(sec_count4)
	begin
		case(sec_count4)
			3'b000:	sec_seg4 <= 8'b00000011; //0
			3'b001:	sec_seg4 <= 8'b10011111; //1
			3'b010:	sec_seg4 <= 8'b00100101; //2
			3'b011:	sec_seg4 <= 8'b00001101; //3
			3'b100:	sec_seg4 <= 8'b10011001; //4
			3'b101:	sec_seg4 <= 8'b01001001; //5
		   default: sec_seg4 <= 8'b11111111; //black
		 endcase			
	end

	always @(posedge clk) //扫描信号提取
if(scan==19'b1111111111111111111)
  begin
  scan<=19'b0000000000000000000;
  end
else
	begin
		scan<=scan + 1;
	end
	
	always @(scan_clk or	sec_seg1 or sec_seg2 or sec_seg3 or sec_seg4) //扫描输出
	begin
		case(scan_clk)
			2'b00:
				begin
					seg <= sec_seg1;
					an   <= 4'b1110;
				end
			2'b01:
				begin
					seg <= sec_seg2;
					an   <= 4'b1101;
				end
			2'b10:
				begin
					seg <= sec_seg3;
					an   <= 4'b1011;
				end
			2'b11:
				begin
					seg <= sec_seg4;
					an   <= 4'b0111;
				end	
			default:
				begin
					seg <= 8'b11111111;//black
					an   <= 4'b1111;
				end		
		endcase		
  	end	     
endmodule