work__info

This is version 1.4 of the MC8051 IP core.

m255
13
cModel Technology
dG:\mc8051_design\mc8051_design\msim
T_opt
V;0kJbOzlA5<h?m;P`a<;?3
04 21 0 work tb_mc8051_top_sim_cfg 1
o-quiet -auto_acc_if_foreign -work work
tExplicit 1
OE;O;6.2b;35
Eaddsub_core
w1175220388
DP work mc8051_p D@ajnA8l=^ZmQbE]9UbS23
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
32
dG:\mc8051_design\mc8051_design\msim
F../vhdl/addsub_core_.vhd
l0
L76
VV:BUlCJPfXJ<hB:Z67F<Z0
OE;C;6.2b;35
tExplicit 1
Astruc
DE work addsub_cy n<an;0Nc78hjH2fm:@YX:0
DE work addsub_ovcy mZ7LZ?0BnFmXETPPnbkFW1
DP work mc8051_p D@ajnA8l=^ZmQbE]9UbS23
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work addsub_core V:BUlCJPfXJ<hB:Z67F<Z0
32
M3 ieee std_logic_1164
M2 ieee std_logic_arith
M1 work mc8051_p
F../vhdl/addsub_core_struc.vhd
l73
L67
VJ?jA_zdZ@kMaL_J:1?9K?2
OE;C;6.2b;35
tExplicit 1
Caddsub_core_struc_cfg
DE work addsub_cy n<an;0Nc78hjH2fm:@YX:0
DE work addsub_ovcy mZ7LZ?0BnFmXETPPnbkFW1
DC work addsub_cy_rtl_cfg li`feVnl8I3@l2z6R5m4Q3
DC work addsub_ovcy_rtl_cfg ADoMRelf343h:^6nOQ`Fe3
DA work addsub_core struc J?jA_zdZ@kMaL_J:1?9K?2
DP work mc8051_p D@ajnA8l=^ZmQbE]9UbS23
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work addsub_core V:BUlCJPfXJ<hB:Z67F<Z0
32
M3 ieee std_logic_1164
M2 ieee std_logic_arith
M1 work mc8051_p
astruc
eaddsub_core
w1175220388
dG:\mc8051_design\mc8051_design\msim
F../vhdl/addsub_core_struc_cfg.vhd
l0
L67
VnDBzjFeG7H]_MK3cH0=FX0
OE;C;6.2b;35
tExplicit 1
Eaddsub_cy
w1175220388
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
32
dG:\mc8051_design\mc8051_design\msim
F../vhdl/addsub_cy_.vhd
l0
L72
Vn<an;0Nc78hjH2fm:@YX:0
OE;C;6.2b;35
tExplicit 1
Artl
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work addsub_cy n<an;0Nc78hjH2fm:@YX:0
32
M2 ieee std_logic_1164
M1 ieee std_logic_arith
F../vhdl/addsub_cy_rtl.vhd
l68
L66
VoTlMOgQ>U=PMOBDbEFhG60
OE;C;6.2b;35
tExplicit 1
Caddsub_cy_rtl_cfg
DA work addsub_cy rtl oTlMOgQ>U=PMOBDbEFhG60
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work addsub_cy n<an;0Nc78hjH2fm:@YX:0
32
M2 ieee std_logic_1164
M1 ieee std_logic_arith
artl
eaddsub_cy
w1175220388
dG:\mc8051_design\mc8051_design\msim
F../vhdl/addsub_cy_rtl_cfg.vhd
l0
L66
Vli`feVnl8I3@l2z6R5m4Q3
OE;C;6.2b;35
tExplicit 1
Eaddsub_ovcy
w1175220388
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
32
dG:\mc8051_design\mc8051_design\msim
F../vhdl/addsub_ovcy_.vhd
l0
L72
VmZ7LZ?0BnFmXETPPnbkFW1
OE;C;6.2b;35
tExplicit 1
Artl
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work addsub_ovcy mZ7LZ?0BnFmXETPPnbkFW1
32
M2 ieee std_logic_1164
M1 ieee std_logic_arith
F../vhdl/addsub_ovcy_rtl.vhd
l68
L66
V^=b:Rk8B7WRYfi@^8RlSi0
OE;C;6.2b;35
tExplicit 1
Caddsub_ovcy_rtl_cfg
DA work addsub_ovcy rtl ^=b:Rk8B7WRYfi@^8RlSi0
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work addsub_ovcy mZ7LZ?0BnFmXETPPnbkFW1
32
M2 ieee std_logic_1164
M1 ieee std_logic_arith
artl
eaddsub_ovcy
w1175220388
dG:\mc8051_design\mc8051_design\msim
F../vhdl/addsub_ovcy_rtl_cfg.vhd
l0
L66
VADoMRelf343h:^6nOQ`Fe3
OE;C;6.2b;35
tExplicit 1
Ealucore
w1175220388
DP work mc8051_p D@ajnA8l=^ZmQbE]9UbS23
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
32
dG:\mc8051_design\mc8051_design\msim
F../vhdl/alucore_.vhd
l0
L73
VJQca7:=9YUP4TJnWjG`o=3
OE;C;6.2b;35
tExplicit 1
Artl
DP work mc8051_p D@ajnA8l=^ZmQbE]9UbS23
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work alucore JQca7:=9YUP4TJnWjG`o=3
32
M3 ieee std_logic_1164
M2 ieee std_logic_arith
M1 work mc8051_p
F../vhdl/alucore_rtl.vhd
l77
L65
VTFP5@OID=XP^EmFzj::lA1
OE;C;6.2b;35
tExplicit 1
Calucore_rtl_cfg
DA work alucore rtl TFP5@OID=XP^EmFzj::lA1
DP work mc8051_p D@ajnA8l=^ZmQbE]9UbS23
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work alucore JQca7:=9YUP4TJnWjG`o=3
32
M3 ieee std_logic_1164
M2 ieee std_logic_arith
M1 work mc8051_p
artl
ealucore
w1175220388
dG:\mc8051_design\mc8051_design\msim
F../vhdl/alucore_rtl_cfg.vhd
l0
L65
VDbB1=AioMzgI1P0HgI5BV2
OE;C;6.2b;35
tExplicit 1
Ealumux
w1175220388
DP work mc8051_p D@ajnA8l=^ZmQbE]9UbS23
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
32
dG:\mc8051_design\mc8051_design\msim
F../vhdl/alumux_.vhd
l0
L74
VPChdmEQ@hQCdb0W=m[:l60
OE;C;6.2b;35
tExplicit 1
Artl
DP work mc8051_p D@ajnA8l=^ZmQbE]9UbS23
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work alumux PChdmEQ@hQCdb0W=m[:l60
32
M3 ieee std_logic_1164
M2 ieee std_logic_arith
M1 work mc8051_p
F../vhdl/alumux_rtl.vhd
l110
L65
VT5:jmjiL:6no=WZLcFgSB0
OE;C;6.2b;35
tExplicit 1
Calumux_rtl_cfg
DA work alumux rtl T5:jmjiL:6no=WZLcFgSB0
DP work mc8051_p D@ajnA8l=^ZmQbE]9UbS23
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work alumux PChdmEQ@hQCdb0W=m[:l60
32
M3 ieee std_logic_1164
M2 ieee std_logic_arith
M1 work mc8051_p
artl
ealumux
w1175220388
dG:\mc8051_design\mc8051_design\msim
F../vhdl/alumux_rtl_cfg.vhd
l0
L65
VfJY6RH1QkZV<ZOz5HL`T[3
OE;C;6.2b;35
tExplicit 1
Ecomb_divider
w1175220388
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
32
dG:\mc8051_design\mc8051_design\msim
F../vhdl/comb_divider_.vhd
l0
L72
VN<RM69X`51JF<^OQdKkV;0
OE;C;6.2b;35
tExplicit 1
Artl
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work comb_divider N<RM69X`51JF<^OQdKkV;0
32
M2 ieee std_logic_1164
M1 ieee std_logic_arith
F../vhdl/comb_divider_rtl.vhd
l68
L66
VbX6za2O=AVffhh>LoiNaZ0
OE;C;6.2b;35
tExplicit 1
Ccomb_divider_rtl_cfg
DA work comb_divider rtl bX6za2O=AVffhh>LoiNaZ0
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work comb_divider N<RM69X`51JF<^OQdKkV;0
32
M2 ieee std_logic_1164
M1 ieee std_logic_arith
artl
ecomb_divider
w1175220388
dG:\mc8051_design\mc8051_design\msim
F../vhdl/comb_divider_rtl_cfg.vhd
l0
L66
VzjUaGz83mejnb_PGVmCcD1
OE;C;6.2b;35
tExplicit 1
Ecomb_mltplr
w1175220388
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
32
dG:\mc8051_design\mc8051_design\msim
F../vhdl/comb_mltplr_.vhd
l0
L72
Vb<8<8?9SUdF8=ZVfE:N:R2
OE;C;6.2b;35
tExplicit 1
Artl
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work comb_mltplr b<8<8?9SUdF8=ZVfE:N:R2
32
M2 ieee std_logic_1164
M1 ieee std_logic_arith
F../vhdl/comb_mltplr_rtl.vhd
l68
L66
VgQda5GY?jS^`7]R6b3d=l3
OE;C;6.2b;35
tExplicit 1
Ccomb_mltplr_rtl_cfg
DA work comb_mltplr rtl gQda5GY?jS^`7]R6b3d=l3
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work comb_mltplr b<8<8?9SUdF8=ZVfE:N:R2
32
M2 ieee std_logic_1164
M1 ieee std_logic_arith
artl
ecomb_mltplr
w1175220388
dG:\mc8051_design\mc8051_design\msim
F../vhdl/comb_mltplr_rtl_cfg.vhd
l0
L66
V`3>@@M3<PXGzhl^L>BQ4;2
OE;C;6.2b;35
tExplicit 1
Econtrol_fsm
w1175220388
DP work mc8051_p D@ajnA8l=^ZmQbE]9UbS23
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
32
dG:\mc8051_design\mc8051_design\msim
F../vhdl/control_fsm_.vhd
l0
L74
VU`Y:W^E5^2JSXDf`T^UX`2
OE;C;6.2b;35
tExplicit 1
Artl
DP work mc8051_p D@ajnA8l=^ZmQbE]9UbS23
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work control_fsm U`Y:W^E5^2JSXDf`T^UX`2
32
M3 ieee std_logic_1164
M2 ieee std_logic_arith
M1 work mc8051_p
F../vhdl/control_fsm_rtl.vhd
l130
L66
VbT99_fHdR@DQoJS6kCI]M3
OE;C;6.2b;35
tExplicit 1
Ccontrol_fsm_rtl_cfg
DA work control_fsm rtl bT99_fHdR@DQoJS6kCI]M3
DP work mc8051_p D@ajnA8l=^ZmQbE]9UbS23
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work control_fsm U`Y:W^E5^2JSXDf`T^UX`2
32
M3 ieee std_logic_1164
M2 ieee std_logic_arith
M1 work mc8051_p
artl
econtrol_fsm
w1175220390
dG:\mc8051_design\mc8051_design\msim
F../vhdl/control_fsm_rtl_cfg.vhd
l0
L66
VLW7k20K`6oLhMjAXO3d<S2
OE;C;6.2b;35
tExplicit 1
Econtrol_mem
w1175220390
DP work mc8051_p D@ajnA8l=^ZmQbE]9UbS23
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
32
dG:\mc8051_design\mc8051_design\msim
F../vhdl/control_mem_.vhd
l0
L75
V2;5IIK760Nhj5h1NajMaW1
OE;C;6.2b;35
tExplicit 1
Artl
DP work mc8051_p D@ajnA8l=^ZmQbE]9UbS23
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work control_mem 2;5IIK760Nhj5h1NajMaW1
32
M3 ieee std_logic_1164
M2 ieee std_logic_arith
M1 work mc8051_p
F../vhdl/control_mem_rtl.vhd
l226
L68
V4^k;QJl:e45`83gQ:c<m13
OE;C;6.2b;35
tExplicit 1
Ccontrol_mem_rtl_cfg
DA work control_mem rtl 4^k;QJl:e45`83gQ:c<m13
DP work mc8051_p D@ajnA8l=^ZmQbE]9UbS23
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work control_mem 2;5IIK760Nhj5h1NajMaW1
32
M3 ieee std_logic_1164
M2 ieee std_logic_arith
M1 work mc8051_p
artl
econtrol_mem
w1175220390
dG:\mc8051_design\mc8051_design\msim
F../vhdl/control_mem_rtl_cfg.vhd
l0
L68
VQI1OT^HPG4bOe_W>84_KM0
OE;C;6.2b;35
tExplicit 1
Edcml_adjust
w1175220390
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
32
dG:\mc8051_design\mc8051_design\msim
F../vhdl/dcml_adjust_.vhd
l0
L72
VT5iLI=DbSY0;h6U::3Y6_0
OE;C;6.2b;35
tExplicit 1
Artl
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work dcml_adjust T5iLI=DbSY0;h6U::3Y6_0
32
M2 ieee std_logic_1164
M1 ieee std_logic_arith
F../vhdl/dcml_adjust_rtl.vhd
l68
L66
VENlI_5UN9CX@=Cfa<>>C_2
OE;C;6.2b;35
tExplicit 1
Cdcml_adjust_rtl_cfg
DA work dcml_adjust rtl ENlI_5UN9CX@=Cfa<>>C_2
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work dcml_adjust T5iLI=DbSY0;h6U::3Y6_0
32
M2 ieee std_logic_1164
M1 ieee std_logic_arith
artl
edcml_adjust
w1175220390
dG:\mc8051_design\mc8051_design\msim
F../vhdl/dcml_adjust_rtl_cfg.vhd
l0
L66
VzC]PjRGicjfKXkzCi6NVi1
OE;C;6.2b;35
tExplicit 1
Emc8051_alu
w1175220390
DP work mc8051_p D@ajnA8l=^ZmQbE]9UbS23
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
32
dG:\mc8051_design\mc8051_design\msim
F../vhdl/mc8051_alu_.vhd
l0
L75
VIW;jNCiC`O:WYZI>E2?]E2
OE;C;6.2b;35
tExplicit 1
Astruc
DE work dcml_adjust T5iLI=DbSY0;h6U::3Y6_0
DE work comb_divider N<RM69X`51JF<^OQdKkV;0
DE work comb_mltplr b<8<8?9SUdF8=ZVfE:N:R2
DE work addsub_core V:BUlCJPfXJ<hB:Z67F<Z0
DE work alucore JQca7:=9YUP4TJnWjG`o=3
DE work alumux PChdmEQ@hQCdb0W=m[:l60
DP work mc8051_p D@ajnA8l=^ZmQbE]9UbS23
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work mc8051_alu IW;jNCiC`O:WYZI>E2?]E2
32
M3 ieee std_logic_1164
M2 ieee std_logic_arith
M1 work mc8051_p
F../vhdl/mc8051_alu_struc.vhd
l92
L67
VRCZ7[IMBBH56XFl4FmFYP0
OE;C;6.2b;35
tExplicit 1