uart_top.tan.qmsg

URAT异步通信接口的VHDL描述

{ "Info" "ITDB_FULL_TPD_RESULT" "RDn DOUT\[6\] 12.638 ns Longest " "Info: Longest tpd from source pin \"RDn\" to destination pin \"DOUT\[6\]\" is 12.638 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.850 ns) 0.850 ns RDn 1 PIN PIN_65 6 " "Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_65; Fanout = 6; PIN Node = 'RDn'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { RDn } "NODE_NAME" } } { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 102 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.475 ns) + CELL(0.150 ns) 6.475 ns Intface:U1\|RbrRDn_r~31 2 COMB LCCOMB_X24_Y9_N0 2 " "Info: 2: + IC(5.475 ns) + CELL(0.150 ns) = 6.475 ns; Loc. = LCCOMB_X24_Y9_N0; Fanout = 2; COMB Node = 'Intface:U1\|RbrRDn_r~31'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "5.625 ns" { RDn Intface:U1|RbrRDn_r~31 } "NODE_NAME" } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 346 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.704 ns) + CELL(0.150 ns) 7.329 ns Intface:U1\|DOUT\[6\]~1508 3 COMB LCCOMB_X22_Y10_N20 1 " "Info: 3: + IC(0.704 ns) + CELL(0.150 ns) = 7.329 ns; Loc. = LCCOMB_X22_Y10_N20; Fanout = 1; COMB Node = 'Intface:U1\|DOUT\[6\]~1508'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.854 ns" { Intface:U1|RbrRDn_r~31 Intface:U1|DOUT[6]~1508 } "NODE_NAME" } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 297 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.242 ns) + CELL(0.245 ns) 8.816 ns Intface:U1\|DOUT\[6\]~1509 4 COMB LCCOMB_X20_Y10_N8 1 " "Info: 4: + IC(1.242 ns) + CELL(0.245 ns) = 8.816 ns; Loc. = LCCOMB_X20_Y10_N8; Fanout = 1; COMB Node = 'Intface:U1\|DOUT\[6\]~1509'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.487 ns" { Intface:U1|DOUT[6]~1508 Intface:U1|DOUT[6]~1509 } "NODE_NAME" } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 297 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.180 ns) + CELL(2.642 ns) 12.638 ns DOUT\[6\] 5 PIN PIN_93 0 " "Info: 5: + IC(1.180 ns) + CELL(2.642 ns) = 12.638 ns; Loc. = PIN_93; Fanout = 0; PIN Node = 'DOUT\[6\]'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.822 ns" { Intface:U1|DOUT[6]~1509 DOUT[6] } "NODE_NAME" } } { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 99 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.037 ns ( 31.94 % ) " "Info: Total cell delay = 4.037 ns ( 31.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.601 ns ( 68.06 % ) " "Info: Total interconnect delay = 8.601 ns ( 68.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "12.638 ns" { RDn Intface:U1|RbrRDn_r~31 Intface:U1|DOUT[6]~1508 Intface:U1|DOUT[6]~1509 DOUT[6] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "12.638 ns" { RDn RDn~combout Intface:U1|RbrRDn_r~31 Intface:U1|DOUT[6]~1508 Intface:U1|DOUT[6]~1509 DOUT[6] } { 0.000ns 0.000ns 5.475ns 0.704ns 1.242ns 1.180ns } { 0.000ns 0.850ns 0.150ns 0.150ns 0.245ns 2.642ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "Intface:U1\|RbrRDn1_r MR MCLK 0.096 ns register " "Info: th for register \"Intface:U1\|RbrRDn1_r\" (data pin = \"MR\", clock pin = \"MCLK\") is 0.096 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "MCLK destination 2.369 ns + Longest register " "Info: + Longest clock path from clock \"MCLK\" to destination register is 2.369 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns MCLK 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'MCLK'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { MCLK } "NODE_NAME" } } { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 94 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns MCLK~clkctrl 2 COMB CLKCTRL_G2 103 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 103; COMB Node = 'MCLK~clkctrl'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.122 ns" { MCLK MCLK~clkctrl } "NODE_NAME" } } { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 94 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.721 ns) + CELL(0.537 ns) 2.369 ns Intface:U1\|RbrRDn1_r 3 REG LCFF_X24_Y9_N15 2 " "Info: 3: + IC(0.721 ns) + CELL(0.537 ns) = 2.369 ns; Loc. = LCFF_X24_Y9_N15; Fanout = 2; REG Node = 'Intface:U1\|RbrRDn1_r'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.258 ns" { MCLK~clkctrl Intface:U1|RbrRDn1_r } "NODE_NAME" } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 354 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.42 % ) " "Info: Total cell delay = 1.526 ns ( 64.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.843 ns ( 35.58 % ) " "Info: Total interconnect delay = 0.843 ns ( 35.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.369 ns" { MCLK MCLK~clkctrl Intface:U1|RbrRDn1_r } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "2.369 ns" { MCLK MCLK~combout MCLK~clkctrl Intface:U1|RbrRDn1_r } { 0.000ns 0.000ns 0.122ns 0.721ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 354 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.539 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.539 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns MR 1 PIN PIN_21 8 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_21; Fanout = 8; PIN Node = 'MR'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { MR } "NODE_NAME" } } { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 93 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.191 ns) + CELL(0.275 ns) 2.455 ns Intface:U1\|RbrRDn_r~32 2 COMB LCCOMB_X24_Y9_N14 1 " "Info: 2: + IC(1.191 ns) + CELL(0.275 ns) = 2.455 ns; Loc. = LCCOMB_X24_Y9_N14; Fanout = 1; COMB Node = 'Intface:U1\|RbrRDn_r~32'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.466 ns" { MR Intface:U1|RbrRDn_r~32 } "NODE_NAME" } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 346 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.539 ns Intface:U1\|RbrRDn1_r 3 REG LCFF_X24_Y9_N15 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.539 ns; Loc. = LCFF_X24_Y9_N15; Fanout = 2; REG Node = 'Intface:U1\|RbrRDn1_r'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.084 ns" { Intface:U1|RbrRDn_r~32 Intface:U1|RbrRDn1_r } "NODE_NAME" } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 354 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.348 ns ( 53.09 % ) " "Info: Total cell delay = 1.348 ns ( 53.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.191 ns ( 46.91 % ) " "Info: Total interconnect delay = 1.191 ns ( 46.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.539 ns" { MR Intface:U1|RbrRDn_r~32 Intface:U1|RbrRDn1_r } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "2.539 ns" { MR MR~combout Intface:U1|RbrRDn_r~32 Intface:U1|RbrRDn1_r } { 0.000ns 0.000ns 1.191ns 0.000ns } { 0.000ns 0.989ns 0.275ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.369 ns" { MCLK MCLK~clkctrl Intface:U1|RbrRDn1_r } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "2.369 ns" { MCLK MCLK~combout MCLK~clkctrl Intface:U1|RbrRDn1_r } { 0.000ns 0.000ns 0.122ns 0.721ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.539 ns" { MR Intface:U1|RbrRDn_r~32 Intface:U1|RbrRDn1_r } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "2.539 ns" { MR MR~combout Intface:U1|RbrRDn_r~32 Intface:U1|RbrRDn1_r } { 0.000ns 0.000ns 1.191ns 0.000ns } { 0.000ns 0.989ns 0.275ns 0.084ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 8 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 30 21:13:57 2008 " "Info: Processing ended: Sun Mar 30 21:13:57 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}