uart_top.tan.qmsg

URAT异步通信接口的VHDL描述

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "ADSn 63 " "Warning: Circuit may not operate. Detected 63 non-operational path(s) clocked by clock \"ADSn\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "Intface:U1\|ADDR_s\[2\] Intface:U1\|LCR\[3\] ADSn 1.512 ns " "Info: Found hold time violation between source  pin or register \"Intface:U1\|ADDR_s\[2\]\" and destination pin or register \"Intface:U1\|LCR\[3\]\" for clock \"ADSn\" (Hold time is 1.512 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "2.691 ns + Largest " "Info: + Largest clock skew is 2.691 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ADSn destination 5.007 ns + Longest register " "Info: + Longest clock path from clock \"ADSn\" to destination register is 5.007 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns ADSn 1 CLK PIN_18 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'ADSn'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { ADSn } "NODE_NAME" } } { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 100 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.101 ns ADSn~clkctrl 2 COMB CLKCTRL_G1 4 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G1; Fanout = 4; COMB Node = 'ADSn~clkctrl'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.122 ns" { ADSn ADSn~clkctrl } "NODE_NAME" } } { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 100 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.040 ns) + CELL(0.150 ns) 2.291 ns Intface:U1\|CS_r 3 REG LCCOMB_X24_Y9_N10 8 " "Info: 3: + IC(1.040 ns) + CELL(0.150 ns) = 2.291 ns; Loc. = LCCOMB_X24_Y9_N10; Fanout = 8; REG Node = 'Intface:U1\|CS_r'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.190 ns" { ADSn~clkctrl Intface:U1|CS_r } "NODE_NAME" } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 335 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.264 ns) + CELL(0.150 ns) 2.705 ns Intface:U1\|WRn_cs~4 4 COMB LCCOMB_X24_Y9_N18 1 " "Info: 4: + IC(0.264 ns) + CELL(0.150 ns) = 2.705 ns; Loc. = LCCOMB_X24_Y9_N18; Fanout = 1; COMB Node = 'Intface:U1\|WRn_cs~4'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.414 ns" { Intface:U1|CS_r Intface:U1|WRn_cs~4 } "NODE_NAME" } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 337 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.040 ns) + CELL(0.000 ns) 3.745 ns Intface:U1\|WRn_cs~4clkctrl 5 COMB CLKCTRL_G7 21 " "Info: 5: + IC(1.040 ns) + CELL(0.000 ns) = 3.745 ns; Loc. = CLKCTRL_G7; Fanout = 21; COMB Node = 'Intface:U1\|WRn_cs~4clkctrl'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.040 ns" { Intface:U1|WRn_cs~4 Intface:U1|WRn_cs~4clkctrl } "NODE_NAME" } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 337 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.725 ns) + CELL(0.537 ns) 5.007 ns Intface:U1\|LCR\[3\] 6 REG LCFF_X18_Y11_N15 5 " "Info: 6: + IC(0.725 ns) + CELL(0.537 ns) = 5.007 ns; Loc. = LCFF_X18_Y11_N15; Fanout = 5; REG Node = 'Intface:U1\|LCR\[3\]'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.262 ns" { Intface:U1|WRn_cs~4clkctrl Intface:U1|LCR[3] } "NODE_NAME" } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 507 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.816 ns ( 36.27 % ) " "Info: Total cell delay = 1.816 ns ( 36.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.191 ns ( 63.73 % ) " "Info: Total interconnect delay = 3.191 ns ( 63.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "5.007 ns" { ADSn ADSn~clkctrl Intface:U1|CS_r Intface:U1|WRn_cs~4 Intface:U1|WRn_cs~4clkctrl Intface:U1|LCR[3] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "5.007 ns" { ADSn ADSn~combout ADSn~clkctrl Intface:U1|CS_r Intface:U1|WRn_cs~4 Intface:U1|WRn_cs~4clkctrl Intface:U1|LCR[3] } { 0.000ns 0.000ns 0.122ns 1.040ns 0.264ns 1.040ns 0.725ns } { 0.000ns 0.979ns 0.000ns 0.150ns 0.150ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ADSn source 2.316 ns - Shortest register " "Info: - Shortest clock path from clock \"ADSn\" to source register is 2.316 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns ADSn 1 CLK PIN_18 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'ADSn'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { ADSn } "NODE_NAME" } } { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 100 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.101 ns ADSn~clkctrl 2 COMB CLKCTRL_G1 4 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G1; Fanout = 4; COMB Node = 'ADSn~clkctrl'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.122 ns" { ADSn ADSn~clkctrl } "NODE_NAME" } } { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 100 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(0.150 ns) 2.316 ns Intface:U1\|ADDR_s\[2\] 3 REG LCCOMB_X18_Y11_N16 17 " "Info: 3: + IC(1.065 ns) + CELL(0.150 ns) = 2.316 ns; Loc. = LCCOMB_X18_Y11_N16; Fanout = 17; REG Node = 'Intface:U1\|ADDR_s\[2\]'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.215 ns" { ADSn~clkctrl Intface:U1|ADDR_s[2] } "NODE_NAME" } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 398 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.129 ns ( 48.75 % ) " "Info: Total cell delay = 1.129 ns ( 48.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.187 ns ( 51.25 % ) " "Info: Total interconnect delay = 1.187 ns ( 51.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.316 ns" { ADSn ADSn~clkctrl Intface:U1|ADDR_s[2] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "2.316 ns" { ADSn ADSn~combout ADSn~clkctrl Intface:U1|ADDR_s[2] } { 0.000ns 0.000ns 0.122ns 1.065ns } { 0.000ns 0.979ns 0.000ns 0.150ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "5.007 ns" { ADSn ADSn~clkctrl Intface:U1|CS_r Intface:U1|WRn_cs~4 Intface:U1|WRn_cs~4clkctrl Intface:U1|LCR[3] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "5.007 ns" { ADSn ADSn~combout ADSn~clkctrl Intface:U1|CS_r Intface:U1|WRn_cs~4 Intface:U1|WRn_cs~4clkctrl Intface:U1|LCR[3] } { 0.000ns 0.000ns 0.122ns 1.040ns 0.264ns 1.040ns 0.725ns } { 0.000ns 0.979ns 0.000ns 0.150ns 0.150ns 0.000ns 0.537ns } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.316 ns" { ADSn ADSn~clkctrl Intface:U1|ADDR_s[2] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "2.316 ns" { ADSn ADSn~combout ADSn~clkctrl Intface:U1|ADDR_s[2] } { 0.000ns 0.000ns 0.122ns 1.065ns } { 0.000ns 0.979ns 0.000ns 0.150ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns - " "Info: - Micro clock to output delay of source is 0.000 ns" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 398 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.445 ns - Shortest register register " "Info: - Shortest register to register delay is 1.445 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Intface:U1\|ADDR_s\[2\] 1 REG LCCOMB_X18_Y11_N16 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X18_Y11_N16; Fanout = 17; REG Node = 'Intface:U1\|ADDR_s\[2\]'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { Intface:U1|ADDR_s[2] } "NODE_NAME" } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 398 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.289 ns) + CELL(0.275 ns) 0.564 ns Intface:U1\|Equal0~82 2 COMB LCCOMB_X18_Y11_N30 7 " "Info: 2: + IC(0.289 ns) + CELL(0.275 ns) = 0.564 ns; Loc. = LCCOMB_X18_Y11_N30; Fanout = 7; COMB Node = 'Intface:U1\|Equal0~82'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.564 ns" { Intface:U1|ADDR_s[2] Intface:U1|Equal0~82 } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/edatool/altera/quartus6.0/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.221 ns) + CELL(0.660 ns) 1.445 ns Intface:U1\|LCR\[3\] 3 REG LCFF_X18_Y11_N15 5 " "Info: 3: + IC(0.221 ns) + CELL(0.660 ns) = 1.445 ns; Loc. = LCFF_X18_Y11_N15; Fanout = 5; REG Node = 'Intface:U1\|LCR\[3\]'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.881 ns" { Intface:U1|Equal0~82 Intface:U1|LCR[3] } "NODE_NAME" } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 507 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.935 ns ( 64.71 % ) " "Info: Total cell delay = 0.935 ns ( 64.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.510 ns ( 35.29 % ) " "Info: Total interconnect delay = 0.510 ns ( 35.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.445 ns" { Intface:U1|ADDR_s[2] Intface:U1|Equal0~82 Intface:U1|LCR[3] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "1.445 ns" { Intface:U1|ADDR_s[2] Intface:U1|Equal0~82 Intface:U1|LCR[3] } { 0.000ns 0.289ns 0.221ns } { 0.000ns 0.275ns 0.660ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 507 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "5.007 ns" { ADSn ADSn~clkctrl Intface:U1|CS_r Intface:U1|WRn_cs~4 Intface:U1|WRn_cs~4clkctrl Intface:U1|LCR[3] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "5.007 ns" { ADSn ADSn~combout ADSn~clkctrl Intface:U1|CS_r Intface:U1|WRn_cs~4 Intface:U1|WRn_cs~4clkctrl Intface:U1|LCR[3] } { 0.000ns 0.000ns 0.122ns 1.040ns 0.264ns 1.040ns 0.725ns } { 0.000ns 0.979ns 0.000ns 0.150ns 0.150ns 0.000ns 0.537ns } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.316 ns" { ADSn ADSn~clkctrl Intface:U1|ADDR_s[2] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "2.316 ns" { ADSn ADSn~combout ADSn~clkctrl Intface:U1|ADDR_s[2] } { 0.000ns 0.000ns 0.122ns 1.065ns } { 0.000ns 0.979ns 0.000ns 0.150ns } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.445 ns" { Intface:U1|ADDR_s[2] Intface:U1|Equal0~82 Intface:U1|LCR[3] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "1.445 ns" { Intface:U1|ADDR_s[2] Intface:U1|Equal0~82 Intface:U1|LCR[3] } { 0.000ns 0.289ns 0.221ns } { 0.000ns 0.275ns 0.660ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "Rxcver:U3\|RxPrtyErr SIN MCLK 6.578 ns register " "Info: tsu for register \"Rxcver:U3\|RxPrtyErr\" (data pin = \"SIN\", clock pin = \"MCLK\") is 6.578 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.986 ns + Longest pin register " "Info: + Longest pin to register delay is 8.986 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.840 ns) 0.840 ns SIN 1 PIN PIN_118 10 " "Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_118; Fanout = 10; PIN Node = 'SIN'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { SIN } "NODE_NAME" } } { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.482 ns) + CELL(0.398 ns) 6.720 ns Rxcver:U3\|Shift_data_Proc~106 2 COMB LCCOMB_X20_Y11_N0 3 " "Info: 2: + IC(5.482 ns) + CELL(0.398 ns) = 6.720 ns; Loc. = LCCOMB_X20_Y11_N0; Fanout = 3; COMB Node = 'Rxcver:U3\|Shift_data_Proc~106'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "5.880 ns" { SIN Rxcver:U3|Shift_data_Proc~106 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.701 ns) + CELL(0.438 ns) 7.859 ns Rxcver:U3\|Selector12~460 3 COMB LCCOMB_X18_Y11_N0 1 " "Info: 3: + IC(0.701 ns) + CELL(0.438 ns) = 7.859 ns; Loc. = LCCOMB_X18_Y11_N0; Fanout = 1; COMB Node = 'Rxcver:U3\|Selector12~460'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.139 ns" { Rxcver:U3|Shift_data_Proc~106 Rxcver:U3|Selector12~460 } "NODE_NAME" } } { "Rxcver.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Rxcver.vhd" 305 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.893 ns) + CELL(0.150 ns) 8.902 ns Rxcver:U3\|Selector12~463 4 COMB LCCOMB_X20_Y11_N18 1 " "Info: 4: + IC(0.893 ns) + CELL(0.150 ns) = 8.902 ns; Loc. = LCCOMB_X20_Y11_N18; Fanout = 1; COMB Node = 'Rxcver:U3\|Selector12~463'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.043 ns" { Rxcver:U3|Selector12~460 Rxcver:U3|Selector12~463 } "NODE_NAME" } } { "Rxcver.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Rxcver.vhd" 305 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 8.986 ns Rxcver:U3\|RxPrtyErr 5 REG LCFF_X20_Y11_N19 4 " "Info: 5: + IC(0.000 ns) + CELL(0.084 ns) = 8.986 ns; Loc. = LCFF_X20_Y11_N19; Fanout = 4; REG Node = 'Rxcver:U3\|RxPrtyErr'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.084 ns" { Rxcver:U3|Selector12~463 Rxcver:U3|RxPrtyErr } "NODE_NAME" } } { "Rxcver.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Rxcver.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.910 ns ( 21.26 % ) " "Info: Total cell delay = 1.910 ns ( 21.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.076 ns ( 78.74 % ) " "Info: Total interconnect delay = 7.076 ns ( 78.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "8.986 ns" { SIN Rxcver:U3|Shift_data_Proc~106 Rxcver:U3|Selector12~460 Rxcver:U3|Selector12~463 Rxcver:U3|RxPrtyErr } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "8.986 ns" { SIN SIN~combout Rxcver:U3|Shift_data_Proc~106 Rxcver:U3|Selector12~460 Rxcver:U3|Selector12~463 Rxcver:U3|RxPrtyErr } { 0.000ns 0.000ns 5.482ns 0.701ns 0.893ns 0.000ns } { 0.000ns 0.840ns 0.398ns 0.438ns 0.150ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "Rxcver.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Rxcver.vhd" 117 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "MCLK destination 2.372 ns - Shortest register " "Info: - Shortest clock path from clock \"MCLK\" to destination register is 2.372 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns MCLK 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'MCLK'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { MCLK } "NODE_NAME" } } { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 94 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns MCLK~clkctrl 2 COMB CLKCTRL_G2 103 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 103; COMB Node = 'MCLK~clkctrl'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.122 ns" { MCLK MCLK~clkctrl } "NODE_NAME" } } { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 94 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.724 ns) + CELL(0.537 ns) 2.372 ns Rxcver:U3\|RxPrtyErr 3 REG LCFF_X20_Y11_N19 4 " "Info: 3: + IC(0.724 ns) + CELL(0.537 ns) = 2.372 ns; Loc. = LCFF_X20_Y11_N19; Fanout = 4; REG Node = 'Rxcver:U3\|RxPrtyErr'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.261 ns" { MCLK~clkctrl Rxcver:U3|RxPrtyErr } "NODE_NAME" } } { "Rxcver.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Rxcver.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.33 % ) " "Info: Total cell delay = 1.526 ns ( 64.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.846 ns ( 35.67 % ) " "Info: Total interconnect delay = 0.846 ns ( 35.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.372 ns" { MCLK MCLK~clkctrl Rxcver:U3|RxPrtyErr } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "2.372 ns" { MCLK MCLK~combout MCLK~clkctrl Rxcver:U3|RxPrtyErr } { 0.000ns 0.000ns 0.122ns 0.724ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "8.986 ns" { SIN Rxcver:U3|Shift_data_Proc~106 Rxcver:U3|Selector12~460 Rxcver:U3|Selector12~463 Rxcver:U3|RxPrtyErr } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "8.986 ns" { SIN SIN~combout Rxcver:U3|Shift_data_Proc~106 Rxcver:U3|Selector12~460 Rxcver:U3|Selector12~463 Rxcver:U3|RxPrtyErr } { 0.000ns 0.000ns 5.482ns 0.701ns 0.893ns 0.000ns } { 0.000ns 0.840ns 0.398ns 0.438ns 0.150ns 0.084ns } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.372 ns" { MCLK MCLK~clkctrl Rxcver:U3|RxPrtyErr } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "2.372 ns" { MCLK MCLK~combout MCLK~clkctrl Rxcver:U3|RxPrtyErr } { 0.000ns 0.000ns 0.122ns 0.724ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "ADSn DOUT\[2\] Intface:U1\|ADDR_s\[1\] 10.713 ns register " "Info: tco from clock \"ADSn\" to destination pin \"DOUT\[2\]\" through register \"Intface:U1\|ADDR_s\[1\]\" is 10.713 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ADSn source 2.314 ns + Longest register " "Info: + Longest clock path from clock \"ADSn\" to source register is 2.314 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns ADSn 1 CLK PIN_18 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'ADSn'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { ADSn } "NODE_NAME" } } { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 100 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.101 ns ADSn~clkctrl 2 COMB CLKCTRL_G1 4 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G1; Fanout = 4; COMB Node = 'ADSn~clkctrl'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.122 ns" { ADSn ADSn~clkctrl } "NODE_NAME" } } { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 100 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.063 ns) + CELL(0.150 ns) 2.314 ns Intface:U1\|ADDR_s\[1\] 3 REG LCCOMB_X18_Y11_N4 17 " "Info: 3: + IC(1.063 ns) + CELL(0.150 ns) = 2.314 ns; Loc. = LCCOMB_X18_Y11_N4; Fanout = 17; REG Node = 'Intface:U1\|ADDR_s\[1\]'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.213 ns" { ADSn~clkctrl Intface:U1|ADDR_s[1] } "NODE_NAME" } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 398 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.129 ns ( 48.79 % ) " "Info: Total cell delay = 1.129 ns ( 48.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.185 ns ( 51.21 % ) " "Info: Total interconnect delay = 1.185 ns ( 51.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.314 ns" { ADSn ADSn~clkctrl Intface:U1|ADDR_s[1] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "2.314 ns" { ADSn ADSn~combout ADSn~clkctrl Intface:U1|ADDR_s[1] } { 0.000ns 0.000ns 0.122ns 1.063ns } { 0.000ns 0.979ns 0.000ns 0.150ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 398 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.399 ns + Longest register pin " "Info: + Longest register to pin delay is 8.399 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Intface:U1\|ADDR_s\[1\] 1 REG LCCOMB_X18_Y11_N4 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X18_Y11_N4; Fanout = 17; REG Node = 'Intface:U1\|ADDR_s\[1\]'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { Intface:U1|ADDR_s[1] } "NODE_NAME" } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 398 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.485 ns) + CELL(0.376 ns) 0.861 ns Intface:U1\|Equal0~81 2 COMB LCCOMB_X18_Y11_N28 13 " "Info: 2: + IC(0.485 ns) + CELL(0.376 ns) = 0.861 ns; Loc. = LCCOMB_X18_Y11_N28; Fanout = 13; COMB Node = 'Intface:U1\|Equal0~81'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.861 ns" { Intface:U1|ADDR_s[1] Intface:U1|Equal0~81 } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/edatool/altera/quartus6.0/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.654 ns) + CELL(0.438 ns) 2.953 ns Intface:U1\|DOUT\[2\]~1494 3 COMB LCCOMB_X21_Y11_N28 1 " "Info: 3: + IC(1.654 ns) + CELL(0.438 ns) = 2.953 ns; Loc. = LCCOMB_X21_Y11_N28; Fanout = 1; COMB Node = 'Intface:U1\|DOUT\[2\]~1494'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.092 ns" { Intface:U1|Equal0~81 Intface:U1|DOUT[2]~1494 } "NODE_NAME" } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 297 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.982 ns) + CELL(0.149 ns) 4.084 ns Intface:U1\|DOUT\[2\]~1495 4 COMB LCCOMB_X24_Y9_N6 1 " "Info: 4: + IC(0.982 ns) + CELL(0.149 ns) = 4.084 ns; Loc. = LCCOMB_X24_Y9_N6; Fanout = 1; COMB Node = 'Intface:U1\|DOUT\[2\]~1495'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.131 ns" { Intface:U1|DOUT[2]~1494 Intface:U1|DOUT[2]~1495 } "NODE_NAME" } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 297 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.274 ns) + CELL(0.438 ns) 4.796 ns Intface:U1\|DOUT\[2\]~1496 5 COMB LCCOMB_X24_Y9_N20 1 " "Info: 5: + IC(0.274 ns) + CELL(0.438 ns) = 4.796 ns; Loc. = LCCOMB_X24_Y9_N20; Fanout = 1; COMB Node = 'Intface:U1\|DOUT\[2\]~1496'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.712 ns" { Intface:U1|DOUT[2]~1495 Intface:U1|DOUT[2]~1496 } "NODE_NAME" } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 297 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.961 ns) + CELL(2.642 ns) 8.399 ns DOUT\[2\] 6 PIN PIN_87 0 " "Info: 6: + IC(0.961 ns) + CELL(2.642 ns) = 8.399 ns; Loc. = PIN_87; Fanout = 0; PIN Node = 'DOUT\[2\]'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.603 ns" { Intface:U1|DOUT[2]~1496 DOUT[2] } "NODE_NAME" } } { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 99 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.043 ns ( 48.14 % ) " "Info: Total cell delay = 4.043 ns ( 48.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.356 ns ( 51.86 % ) " "Info: Total interconnect delay = 4.356 ns ( 51.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "8.399 ns" { Intface:U1|ADDR_s[1] Intface:U1|Equal0~81 Intface:U1|DOUT[2]~1494 Intface:U1|DOUT[2]~1495 Intface:U1|DOUT[2]~1496 DOUT[2] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "8.399 ns" { Intface:U1|ADDR_s[1] Intface:U1|Equal0~81 Intface:U1|DOUT[2]~1494 Intface:U1|DOUT[2]~1495 Intface:U1|DOUT[2]~1496 DOUT[2] } { 0.000ns 0.485ns 1.654ns 0.982ns 0.274ns 0.961ns } { 0.000ns 0.376ns 0.438ns 0.149ns 0.438ns 2.642ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.314 ns" { ADSn ADSn~clkctrl Intface:U1|ADDR_s[1] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "2.314 ns" { ADSn ADSn~combout ADSn~clkctrl Intface:U1|ADDR_s[1] } { 0.000ns 0.000ns 0.122ns 1.063ns } { 0.000ns 0.979ns 0.000ns 0.150ns } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "8.399 ns" { Intface:U1|ADDR_s[1] Intface:U1|Equal0~81 Intface:U1|DOUT[2]~1494 Intface:U1|DOUT[2]~1495 Intface:U1|DOUT[2]~1496 DOUT[2] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "8.399 ns" { Intface:U1|ADDR_s[1] Intface:U1|Equal0~81 Intface:U1|DOUT[2]~1494 Intface:U1|DOUT[2]~1495 Intface:U1|DOUT[2]~1496 DOUT[2] } { 0.000ns 0.485ns 1.654ns 0.982ns 0.274ns 0.961ns } { 0.000ns 0.376ns 0.438ns 0.149ns 0.438ns 2.642ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}