uart_top.tan.qmsg

URAT异步通信接口的VHDL描述

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "MCLK " "Info: Assuming node \"MCLK\" is an undefined clock" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 94 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "MCLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ADSn " "Info: Assuming node \"ADSn\" is an undefined clock" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 100 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "ADSn" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "WRn " "Info: Assuming node \"WRn\" is an undefined clock" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 103 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "WRn" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "Intface:U1\|CS_r " "Info: Detected ripple clock \"Intface:U1\|CS_r\" as buffer" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 335 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "Intface:U1\|CS_r" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Intface:U1\|WRn_cs~4 " "Info: Detected gated clock \"Intface:U1\|WRn_cs~4\" as buffer" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 337 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "Intface:U1\|WRn_cs~4" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "MCLK register Rxcver:U3\|RbrDataRDY register Intface:U1\|Int_State.int0 272.26 MHz 3.673 ns Internal " "Info: Clock \"MCLK\" has Internal fmax of 272.26 MHz between source register \"Rxcver:U3\|RbrDataRDY\" and destination register \"Intface:U1\|Int_State.int0\" (period= 3.673 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.459 ns + Longest register register " "Info: + Longest register to register delay is 3.459 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Rxcver:U3\|RbrDataRDY 1 REG LCFF_X21_Y10_N9 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y10_N9; Fanout = 6; REG Node = 'Rxcver:U3\|RbrDataRDY'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { Rxcver:U3|RbrDataRDY } "NODE_NAME" } } { "Rxcver.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Rxcver.vhd" 246 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.789 ns) + CELL(0.150 ns) 0.939 ns Intface:U1\|Int_Arbit_Proc~1 2 COMB LCCOMB_X21_Y11_N2 4 " "Info: 2: + IC(0.789 ns) + CELL(0.150 ns) = 0.939 ns; Loc. = LCCOMB_X21_Y11_N2; Fanout = 4; COMB Node = 'Intface:U1\|Int_Arbit_Proc~1'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.939 ns" { Rxcver:U3|RbrDataRDY Intface:U1|Int_Arbit_Proc~1 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.270 ns) + CELL(0.376 ns) 1.585 ns Intface:U1\|Selector1~413 3 COMB LCCOMB_X21_Y11_N10 3 " "Info: 3: + IC(0.270 ns) + CELL(0.376 ns) = 1.585 ns; Loc. = LCCOMB_X21_Y11_N10; Fanout = 3; COMB Node = 'Intface:U1\|Selector1~413'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.646 ns" { Intface:U1|Int_Arbit_Proc~1 Intface:U1|Selector1~413 } "NODE_NAME" } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 576 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.711 ns) + CELL(0.275 ns) 2.571 ns Intface:U1\|Selector1~414 4 COMB LCCOMB_X21_Y10_N14 2 " "Info: 4: + IC(0.711 ns) + CELL(0.275 ns) = 2.571 ns; Loc. = LCCOMB_X21_Y10_N14; Fanout = 2; COMB Node = 'Intface:U1\|Selector1~414'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.986 ns" { Intface:U1|Selector1~413 Intface:U1|Selector1~414 } "NODE_NAME" } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 576 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.228 ns) + CELL(0.660 ns) 3.459 ns Intface:U1\|Int_State.int0 5 REG LCFF_X21_Y10_N27 3 " "Info: 5: + IC(0.228 ns) + CELL(0.660 ns) = 3.459 ns; Loc. = LCFF_X21_Y10_N27; Fanout = 3; REG Node = 'Intface:U1\|Int_State.int0'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.888 ns" { Intface:U1|Selector1~414 Intface:U1|Int_State.int0 } "NODE_NAME" } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 572 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.461 ns ( 42.24 % ) " "Info: Total cell delay = 1.461 ns ( 42.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.998 ns ( 57.76 % ) " "Info: Total interconnect delay = 1.998 ns ( 57.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.459 ns" { Rxcver:U3|RbrDataRDY Intface:U1|Int_Arbit_Proc~1 Intface:U1|Selector1~413 Intface:U1|Selector1~414 Intface:U1|Int_State.int0 } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "3.459 ns" { Rxcver:U3|RbrDataRDY Intface:U1|Int_Arbit_Proc~1 Intface:U1|Selector1~413 Intface:U1|Selector1~414 Intface:U1|Int_State.int0 } { 0.000ns 0.789ns 0.270ns 0.711ns 0.228ns } { 0.000ns 0.150ns 0.376ns 0.275ns 0.660ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "MCLK destination 2.368 ns + Shortest register " "Info: + Shortest clock path from clock \"MCLK\" to destination register is 2.368 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns MCLK 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'MCLK'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { MCLK } "NODE_NAME" } } { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 94 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns MCLK~clkctrl 2 COMB CLKCTRL_G2 103 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 103; COMB Node = 'MCLK~clkctrl'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.122 ns" { MCLK MCLK~clkctrl } "NODE_NAME" } } { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 94 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.720 ns) + CELL(0.537 ns) 2.368 ns Intface:U1\|Int_State.int0 3 REG LCFF_X21_Y10_N27 3 " "Info: 3: + IC(0.720 ns) + CELL(0.537 ns) = 2.368 ns; Loc. = LCFF_X21_Y10_N27; Fanout = 3; REG Node = 'Intface:U1\|Int_State.int0'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.257 ns" { MCLK~clkctrl Intface:U1|Int_State.int0 } "NODE_NAME" } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 572 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.44 % ) " "Info: Total cell delay = 1.526 ns ( 64.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.842 ns ( 35.56 % ) " "Info: Total interconnect delay = 0.842 ns ( 35.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.368 ns" { MCLK MCLK~clkctrl Intface:U1|Int_State.int0 } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "2.368 ns" { MCLK MCLK~combout MCLK~clkctrl Intface:U1|Int_State.int0 } { 0.000ns 0.000ns 0.122ns 0.720ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "MCLK source 2.368 ns - Longest register " "Info: - Longest clock path from clock \"MCLK\" to source register is 2.368 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns MCLK 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'MCLK'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { MCLK } "NODE_NAME" } } { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 94 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns MCLK~clkctrl 2 COMB CLKCTRL_G2 103 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 103; COMB Node = 'MCLK~clkctrl'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.122 ns" { MCLK MCLK~clkctrl } "NODE_NAME" } } { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 94 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.720 ns) + CELL(0.537 ns) 2.368 ns Rxcver:U3\|RbrDataRDY 3 REG LCFF_X21_Y10_N9 6 " "Info: 3: + IC(0.720 ns) + CELL(0.537 ns) = 2.368 ns; Loc. = LCFF_X21_Y10_N9; Fanout = 6; REG Node = 'Rxcver:U3\|RbrDataRDY'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.257 ns" { MCLK~clkctrl Rxcver:U3|RbrDataRDY } "NODE_NAME" } } { "Rxcver.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Rxcver.vhd" 246 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.44 % ) " "Info: Total cell delay = 1.526 ns ( 64.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.842 ns ( 35.56 % ) " "Info: Total interconnect delay = 0.842 ns ( 35.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.368 ns" { MCLK MCLK~clkctrl Rxcver:U3|RbrDataRDY } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "2.368 ns" { MCLK MCLK~combout MCLK~clkctrl Rxcver:U3|RbrDataRDY } { 0.000ns 0.000ns 0.122ns 0.720ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.368 ns" { MCLK MCLK~clkctrl Intface:U1|Int_State.int0 } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "2.368 ns" { MCLK MCLK~combout MCLK~clkctrl Intface:U1|Int_State.int0 } { 0.000ns 0.000ns 0.122ns 0.720ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.368 ns" { MCLK MCLK~clkctrl Rxcver:U3|RbrDataRDY } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "2.368 ns" { MCLK MCLK~combout MCLK~clkctrl Rxcver:U3|RbrDataRDY } { 0.000ns 0.000ns 0.122ns 0.720ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "Rxcver.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Rxcver.vhd" 246 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 572 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.459 ns" { Rxcver:U3|RbrDataRDY Intface:U1|Int_Arbit_Proc~1 Intface:U1|Selector1~413 Intface:U1|Selector1~414 Intface:U1|Int_State.int0 } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "3.459 ns" { Rxcver:U3|RbrDataRDY Intface:U1|Int_Arbit_Proc~1 Intface:U1|Selector1~413 Intface:U1|Selector1~414 Intface:U1|Int_State.int0 } { 0.000ns 0.789ns 0.270ns 0.711ns 0.228ns } { 0.000ns 0.150ns 0.376ns 0.275ns 0.660ns } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.368 ns" { MCLK MCLK~clkctrl Intface:U1|Int_State.int0 } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "2.368 ns" { MCLK MCLK~combout MCLK~clkctrl Intface:U1|Int_State.int0 } { 0.000ns 0.000ns 0.122ns 0.720ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.368 ns" { MCLK MCLK~clkctrl Rxcver:U3|RbrDataRDY } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "2.368 ns" { MCLK MCLK~combout MCLK~clkctrl Rxcver:U3|RbrDataRDY } { 0.000ns 0.000ns 0.122ns 0.720ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "WRn " "Info: No valid register-to-register data paths exist for clock \"WRn\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}