uart_top.tan.qmsg

URAT异步通信接口的VHDL描述

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 30 21:13:56 2008 " "Info: Processing started: Sun Mar 30 21:13:56 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off UART_top -c UART_top --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off UART_top -c UART_top --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "Intface:U1\|ADDR_s\[1\] " "Warning: Node \"Intface:U1\|ADDR_s\[1\]\" is a latch" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 398 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "Intface:U1\|ADDR_s\[2\] " "Warning: Node \"Intface:U1\|ADDR_s\[2\]\" is a latch" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 398 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "Intface:U1\|ADDR_s\[0\] " "Warning: Node \"Intface:U1\|ADDR_s\[0\]\" is a latch" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 398 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "Intface:U1\|CS_r " "Warning: Node \"Intface:U1\|CS_r\" is a latch" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 335 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}