uart_top.fit.qmsg

URAT异步通信接口的VHDL描述

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.144 ns register register " "Info: Estimated most critical path is register to register delay of 4.144 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Intface:U1\|MsrRDn2_r 1 REG LAB_X21_Y10 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X21_Y10; Fanout = 5; REG Node = 'Intface:U1\|MsrRDn2_r'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { Intface:U1|MsrRDn2_r } "NODE_NAME" } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 359 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.376 ns) + CELL(0.438 ns) 0.814 ns Intface:U1\|MsrRDn_re~0 2 COMB LAB_X22_Y10 6 " "Info: 2: + IC(0.376 ns) + CELL(0.438 ns) = 0.814 ns; Loc. = LAB_X22_Y10; Fanout = 6; COMB Node = 'Intface:U1\|MsrRDn_re~0'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.814 ns" { Intface:U1|MsrRDn2_r Intface:U1|MsrRDn_re~0 } "NODE_NAME" } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 313 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.336 ns) + CELL(0.420 ns) 1.570 ns Intface:U1\|Selector1~410 3 COMB LAB_X21_Y10 1 " "Info: 3: + IC(0.336 ns) + CELL(0.420 ns) = 1.570 ns; Loc. = LAB_X21_Y10; Fanout = 1; COMB Node = 'Intface:U1\|Selector1~410'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.756 ns" { Intface:U1|MsrRDn_re~0 Intface:U1|Selector1~410 } "NODE_NAME" } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 576 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.127 ns) + CELL(0.438 ns) 2.135 ns Intface:U1\|Selector1~412 4 COMB LAB_X21_Y10 1 " "Info: 4: + IC(0.127 ns) + CELL(0.438 ns) = 2.135 ns; Loc. = LAB_X21_Y10; Fanout = 1; COMB Node = 'Intface:U1\|Selector1~412'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.565 ns" { Intface:U1|Selector1~410 Intface:U1|Selector1~412 } "NODE_NAME" } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 576 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.127 ns) + CELL(0.410 ns) 2.672 ns Intface:U1\|Int_State.idle~6 5 COMB LAB_X21_Y10 2 " "Info: 5: + IC(0.127 ns) + CELL(0.410 ns) = 2.672 ns; Loc. = LAB_X21_Y10; Fanout = 2; COMB Node = 'Intface:U1\|Int_State.idle~6'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.537 ns" { Intface:U1|Selector1~412 Intface:U1|Int_State.idle~6 } "NODE_NAME" } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 572 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.127 ns) + CELL(0.438 ns) 3.237 ns Intface:U1\|Selector1~414 6 COMB LAB_X21_Y10 2 " "Info: 6: + IC(0.127 ns) + CELL(0.438 ns) = 3.237 ns; Loc. = LAB_X21_Y10; Fanout = 2; COMB Node = 'Intface:U1\|Selector1~414'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.565 ns" { Intface:U1|Int_State.idle~6 Intface:U1|Selector1~414 } "NODE_NAME" } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 576 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.247 ns) + CELL(0.660 ns) 4.144 ns Intface:U1\|Int_State.int0 7 REG LAB_X21_Y10 3 " "Info: 7: + IC(0.247 ns) + CELL(0.660 ns) = 4.144 ns; Loc. = LAB_X21_Y10; Fanout = 3; REG Node = 'Intface:U1\|Int_State.int0'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.907 ns" { Intface:U1|Selector1~414 Intface:U1|Int_State.int0 } "NODE_NAME" } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 572 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.804 ns ( 67.66 % ) " "Info: Total cell delay = 2.804 ns ( 67.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.340 ns ( 32.34 % ) " "Info: Total interconnect delay = 1.340 ns ( 32.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "4.144 ns" { Intface:U1|MsrRDn2_r Intface:U1|MsrRDn_re~0 Intface:U1|Selector1~410 Intface:U1|Selector1~412 Intface:U1|Int_State.idle~6 Intface:U1|Selector1~414 Intface:U1|Int_State.int0 } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 2 " "Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 2%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x14_y0 x28_y14 " "Info: The peak interconnect region extends from location x14_y0 to location x28_y14" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}