uart_top.fit.qmsg

URAT异步通信接口的VHDL描述

{ "Info" "IFIOMGR_PINS_MISSING_LOCATION_INFO" "37 37 " "Info: No exact pin location assignment(s) for 37 pins of 37 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DOUT\[0\] " "Info: Pin DOUT\[0\] not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 99 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "DOUT\[0\]" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DOUT[0] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DOUT[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DOUT\[1\] " "Info: Pin DOUT\[1\] not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 99 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "DOUT\[1\]" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DOUT[1] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DOUT[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DOUT\[2\] " "Info: Pin DOUT\[2\] not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 99 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "DOUT\[2\]" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DOUT[2] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DOUT[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DOUT\[3\] " "Info: Pin DOUT\[3\] not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 99 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "DOUT\[3\]" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DOUT[3] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DOUT[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DOUT\[4\] " "Info: Pin DOUT\[4\] not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 99 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "DOUT\[4\]" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DOUT[4] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DOUT[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DOUT\[5\] " "Info: Pin DOUT\[5\] not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 99 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "DOUT\[5\]" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DOUT[5] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DOUT[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DOUT\[6\] " "Info: Pin DOUT\[6\] not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 99 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "DOUT\[6\]" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DOUT[6] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DOUT[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DOUT\[7\] " "Info: Pin DOUT\[7\] not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 99 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "DOUT\[7\]" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DOUT[7] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DOUT[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DDIS " "Info: Pin DDIS not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 104 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "DDIS" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DDIS } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DDIS } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "INTR " "Info: Pin INTR not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 105 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "INTR" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { INTR } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { INTR } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RxRDYn " "Info: Pin RxRDYn not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 109 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "RxRDYn" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { RxRDYn } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { RxRDYn } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SOUT " "Info: Pin SOUT not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 112 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "SOUT" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { SOUT } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { SOUT } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "TxRDYn " "Info: Pin TxRDYn not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 113 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "TxRDYn" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { TxRDYn } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { TxRDYn } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DTRn " "Info: Pin DTRn not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 120 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "DTRn" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DTRn } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DTRn } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RTSn " "Info: Pin RTSn not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 121 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "RTSn" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { RTSn } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { RTSn } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RDn " "Info: Pin RDn not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 102 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "RDn" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { RDn } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { RDn } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MR " "Info: Pin MR not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 93 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "MR" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { MR } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { MR } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A\[1\] " "Info: Pin A\[1\] not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 97 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "A\[1\]" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { A[1] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { A[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "ADSn " "Info: Pin ADSn not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 100 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "ADSn" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { ADSn } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { ADSn } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A\[0\] " "Info: Pin A\[0\] not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 97 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "A\[0\]" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { A[0] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { A[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A\[2\] " "Info: Pin A\[2\] not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 97 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "A\[2\]" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { A[2] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { A[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MCLK " "Info: Pin MCLK not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 94 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "MCLK" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { MCLK } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { MCLK } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CTSn " "Info: Pin CTSn not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 117 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "CTSn" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { CTSn } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { CTSn } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CS " "Info: Pin CS not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 101 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "CS" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { CS } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { CS } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DSRn " "Info: Pin DSRn not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 118 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "DSRn" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DSRn } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DSRn } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RIn " "Info: Pin RIn not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 119 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "RIn" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { RIn } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { RIn } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DCDn " "Info: Pin DCDn not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 116 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "DCDn" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DCDn } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DCDn } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DIN\[6\] " "Info: Pin DIN\[6\] not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 98 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "DIN\[6\]" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DIN[6] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DIN[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "WRn " "Info: Pin WRn not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 103 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "WRn" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { WRn } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { WRn } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DIN\[0\] " "Info: Pin DIN\[0\] not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 98 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "DIN\[0\]" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DIN[0] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DIN[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DIN\[1\] " "Info: Pin DIN\[1\] not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 98 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "DIN\[1\]" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DIN[1] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DIN[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DIN\[2\] " "Info: Pin DIN\[2\] not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 98 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "DIN\[2\]" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DIN[2] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DIN[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DIN\[3\] " "Info: Pin DIN\[3\] not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 98 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "DIN\[3\]" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DIN[3] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DIN[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SIN " "Info: Pin SIN not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 108 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "SIN" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { SIN } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { SIN } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DIN\[5\] " "Info: Pin DIN\[5\] not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 98 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "DIN\[5\]" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DIN[5] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DIN[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DIN\[4\] " "Info: Pin DIN\[4\] not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 98 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "DIN\[4\]" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DIN[4] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DIN[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DIN\[7\] " "Info: Pin DIN\[7\] not assigned to an exact location on the device" {  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 98 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "DIN\[7\]" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DIN[7] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { DIN[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "MCLK (placed in PIN 17 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node MCLK (placed in PIN 17 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0}  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 94 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "MCLK" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { MCLK } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { MCLK } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ADSn (placed in PIN 18 (CLK1, LVDSCLK0n, Input)) " "Info: Automatically promoted node ADSn (placed in PIN 18 (CLK1, LVDSCLK0n, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G1 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0}  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 100 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "ADSn" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { ADSn } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { ADSn } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "Intface:U1\|WRn_cs~4  " "Info: Automatically promoted node Intface:U1\|WRn_cs~4 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0}  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 337 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "Intface:U1\|WRn_cs~4" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { Intface:U1|WRn_cs~4 } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { Intface:U1|WRn_cs~4 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "MR (placed in PIN 21 (CLK2, LVDSCLK1p, Input)) " "Info: Automatically promoted node MR (placed in PIN 21 (CLK2, LVDSCLK1p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Intface:U1\|RbrRDn_r~31 " "Info: Destination node Intface:U1\|RbrRDn_r~31" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 346 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "Intface:U1\|RbrRDn_r~31" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { Intface:U1|RbrRDn_r~31 } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { Intface:U1|RbrRDn_r~31 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Intface:U1\|ThrWRn_r~21 " "Info: Destination node Intface:U1\|ThrWRn_r~21" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 345 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "Intface:U1\|ThrWRn_r~21" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { Intface:U1|ThrWRn_r~21 } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { Intface:U1|ThrWRn_r~21 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Intface:U1\|RbrRDn_r~32 " "Info: Destination node Intface:U1\|RbrRDn_r~32" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 346 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "Intface:U1\|RbrRDn_r~32" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { Intface:U1|RbrRDn_r~32 } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { Intface:U1|RbrRDn_r~32 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Intface:U1\|ADDR_s\[1\] " "Info: Destination node Intface:U1\|ADDR_s\[1\]" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 398 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "Intface:U1\|ADDR_s\[1\]" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { Intface:U1|ADDR_s[1] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { Intface:U1|ADDR_s[1] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Intface:U1\|ADDR_s\[0\] " "Info: Destination node Intface:U1\|ADDR_s\[0\]" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 398 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "Intface:U1\|ADDR_s\[0\]" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { Intface:U1|ADDR_s[0] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { Intface:U1|ADDR_s[0] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Intface:U1\|ADDR_s\[2\] " "Info: Destination node Intface:U1\|ADDR_s\[2\]" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 398 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "Intface:U1\|ADDR_s\[2\]" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { Intface:U1|ADDR_s[2] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { Intface:U1|ADDR_s[2] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Intface:U1\|CS_r " "Info: Destination node Intface:U1\|CS_r" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 335 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "Intface:U1\|CS_r" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { Intface:U1|CS_r } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { Intface:U1|CS_r } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0}  } { { "UART_top.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 93 -1 0 } } { "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/edatool/altera/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "MR" } } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { MR } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { MR } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0}