uart_top.map.qmsg

URAT异步通信接口的VHDL描述

{ "Warning" "WSGN_SEARCH_FILE" "Txmitt.vhd 2 1 " "Warning: Using design file Txmitt.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Txmitt-Txmitt_a " "Info: Found design unit 1: Txmitt-Txmitt_a" {  } { { "Txmitt.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Txmitt.vhd" 109 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 Txmitt " "Info: Found entity 1: Txmitt" {  } { { "Txmitt.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Txmitt.vhd" 85 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Txmitt Txmitt:U4 " "Info: Elaborating entity \"Txmitt\" for hierarchy \"Txmitt:U4\"" {  } { { "UART_top.vhd" "U4" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/UART_top.vhd" 350 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|Uart_top\|Txmitt:U4\|Tx_State 6 " "Info: State machine \"\|Uart_top\|Txmitt:U4\|Tx_State\" contains 6 states" {  } { { "Txmitt.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Txmitt.vhd" 134 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|Uart_top\|Rxcver:U3\|Rx_State 4 " "Info: State machine \"\|Uart_top\|Rxcver:U3\|Rx_State\" contains 4 states" {  } { { "Rxcver.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Rxcver.vhd" 144 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|Uart_top\|Intface:U1\|Int_State 5 " "Info: State machine \"\|Uart_top\|Intface:U1\|Int_State\" contains 5 states" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 373 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|Uart_top\|Txmitt:U4\|Tx_State " "Info: Selected Auto state machine encoding method for state machine \"\|Uart_top\|Txmitt:U4\|Tx_State\"" {  } { { "Txmitt.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Txmitt.vhd" 134 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|Uart_top\|Txmitt:U4\|Tx_State " "Info: Encoding result for state machine \"\|Uart_top\|Txmitt:U4\|Tx_State\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "6 " "Info: Completed encoding using 6 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Txmitt:U4\|Tx_State.stop_halfbit " "Info: Encoded state bit \"Txmitt:U4\|Tx_State.stop_halfbit\"" {  } { { "Txmitt.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Txmitt.vhd" 153 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Txmitt:U4\|Tx_State.stop_2bit " "Info: Encoded state bit \"Txmitt:U4\|Tx_State.stop_2bit\"" {  } { { "Txmitt.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Txmitt.vhd" 153 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Txmitt:U4\|Tx_State.stop_1bit " "Info: Encoded state bit \"Txmitt:U4\|Tx_State.stop_1bit\"" {  } { { "Txmitt.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Txmitt.vhd" 153 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Txmitt:U4\|Tx_State.parity " "Info: Encoded state bit \"Txmitt:U4\|Tx_State.parity\"" {  } { { "Txmitt.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Txmitt.vhd" 153 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Txmitt:U4\|Tx_State.shift " "Info: Encoded state bit \"Txmitt:U4\|Tx_State.shift\"" {  } { { "Txmitt.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Txmitt.vhd" 153 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Txmitt:U4\|Tx_State.start " "Info: Encoded state bit \"Txmitt:U4\|Tx_State.start\"" {  } { { "Txmitt.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Txmitt.vhd" 153 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Uart_top\|Txmitt:U4\|Tx_State.start 000000 " "Info: State \"\|Uart_top\|Txmitt:U4\|Tx_State.start\" uses code string \"000000\"" {  } { { "Txmitt.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Txmitt.vhd" 153 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Uart_top\|Txmitt:U4\|Tx_State.shift 000011 " "Info: State \"\|Uart_top\|Txmitt:U4\|Tx_State.shift\" uses code string \"000011\"" {  } { { "Txmitt.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Txmitt.vhd" 153 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Uart_top\|Txmitt:U4\|Tx_State.parity 000101 " "Info: State \"\|Uart_top\|Txmitt:U4\|Tx_State.parity\" uses code string \"000101\"" {  } { { "Txmitt.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Txmitt.vhd" 153 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Uart_top\|Txmitt:U4\|Tx_State.stop_1bit 001001 " "Info: State \"\|Uart_top\|Txmitt:U4\|Tx_State.stop_1bit\" uses code string \"001001\"" {  } { { "Txmitt.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Txmitt.vhd" 153 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Uart_top\|Txmitt:U4\|Tx_State.stop_2bit 010001 " "Info: State \"\|Uart_top\|Txmitt:U4\|Tx_State.stop_2bit\" uses code string \"010001\"" {  } { { "Txmitt.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Txmitt.vhd" 153 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Uart_top\|Txmitt:U4\|Tx_State.stop_halfbit 100001 " "Info: State \"\|Uart_top\|Txmitt:U4\|Tx_State.stop_halfbit\" uses code string \"100001\"" {  } { { "Txmitt.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Txmitt.vhd" 153 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "Txmitt.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Txmitt.vhd" 134 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|Uart_top\|Rxcver:U3\|Rx_State " "Info: Selected Auto state machine encoding method for state machine \"\|Uart_top\|Rxcver:U3\|Rx_State\"" {  } { { "Rxcver.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Rxcver.vhd" 144 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|Uart_top\|Rxcver:U3\|Rx_State " "Info: Encoding result for state machine \"\|Uart_top\|Rxcver:U3\|Rx_State\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "4 " "Info: Completed encoding using 4 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Rxcver:U3\|Rx_State.stop " "Info: Encoded state bit \"Rxcver:U3\|Rx_State.stop\"" {  } { { "Rxcver.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Rxcver.vhd" 298 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Rxcver:U3\|Rx_State.parity " "Info: Encoded state bit \"Rxcver:U3\|Rx_State.parity\"" {  } { { "Rxcver.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Rxcver.vhd" 298 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Rxcver:U3\|Rx_State.shift " "Info: Encoded state bit \"Rxcver:U3\|Rx_State.shift\"" {  } { { "Rxcver.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Rxcver.vhd" 298 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Rxcver:U3\|Rx_State.idle " "Info: Encoded state bit \"Rxcver:U3\|Rx_State.idle\"" {  } { { "Rxcver.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Rxcver.vhd" 298 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Uart_top\|Rxcver:U3\|Rx_State.idle 0000 " "Info: State \"\|Uart_top\|Rxcver:U3\|Rx_State.idle\" uses code string \"0000\"" {  } { { "Rxcver.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Rxcver.vhd" 298 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Uart_top\|Rxcver:U3\|Rx_State.shift 0011 " "Info: State \"\|Uart_top\|Rxcver:U3\|Rx_State.shift\" uses code string \"0011\"" {  } { { "Rxcver.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Rxcver.vhd" 298 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Uart_top\|Rxcver:U3\|Rx_State.parity 0101 " "Info: State \"\|Uart_top\|Rxcver:U3\|Rx_State.parity\" uses code string \"0101\"" {  } { { "Rxcver.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Rxcver.vhd" 298 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Uart_top\|Rxcver:U3\|Rx_State.stop 1001 " "Info: State \"\|Uart_top\|Rxcver:U3\|Rx_State.stop\" uses code string \"1001\"" {  } { { "Rxcver.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Rxcver.vhd" 298 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "Rxcver.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Rxcver.vhd" 144 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|Uart_top\|Intface:U1\|Int_State " "Info: Selected Auto state machine encoding method for state machine \"\|Uart_top\|Intface:U1\|Int_State\"" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 373 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|Uart_top\|Intface:U1\|Int_State " "Info: Encoding result for state machine \"\|Uart_top\|Intface:U1\|Int_State\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "5 " "Info: Completed encoding using 5 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Intface:U1\|Int_State.int3 " "Info: Encoded state bit \"Intface:U1\|Int_State.int3\"" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 572 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Intface:U1\|Int_State.int2 " "Info: Encoded state bit \"Intface:U1\|Int_State.int2\"" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 572 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Intface:U1\|Int_State.int1 " "Info: Encoded state bit \"Intface:U1\|Int_State.int1\"" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 572 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Intface:U1\|Int_State.int0 " "Info: Encoded state bit \"Intface:U1\|Int_State.int0\"" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 572 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Intface:U1\|Int_State.idle " "Info: Encoded state bit \"Intface:U1\|Int_State.idle\"" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 572 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Uart_top\|Intface:U1\|Int_State.idle 00000 " "Info: State \"\|Uart_top\|Intface:U1\|Int_State.idle\" uses code string \"00000\"" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 572 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Uart_top\|Intface:U1\|Int_State.int0 00011 " "Info: State \"\|Uart_top\|Intface:U1\|Int_State.int0\" uses code string \"00011\"" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 572 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Uart_top\|Intface:U1\|Int_State.int1 00101 " "Info: State \"\|Uart_top\|Intface:U1\|Int_State.int1\" uses code string \"00101\"" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 572 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Uart_top\|Intface:U1\|Int_State.int2 01001 " "Info: State \"\|Uart_top\|Intface:U1\|Int_State.int2\" uses code string \"01001\"" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 572 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Uart_top\|Intface:U1\|Int_State.int3 10001 " "Info: State \"\|Uart_top\|Intface:U1\|Int_State.int3\" uses code string \"10001\"" {  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 572 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 373 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "Txmitt.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Txmitt.vhd" 255 -1 0 } } { "Txmitt.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Txmitt.vhd" 115 -1 0 } } { "Txmitt.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Txmitt.vhd" 111 -1 0 } } { "Rxcver.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Rxcver.vhd" 119 -1 0 } } { "Rxcver.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Rxcver.vhd" 128 -1 0 } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 361 -1 0 } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 360 -1 0 } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 359 -1 0 } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 358 -1 0 } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 357 -1 0 } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 356 -1 0 } } { "Modem.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Modem.vhd" 102 -1 0 } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 355 -1 0 } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 354 -1 0 } } { "Modem.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Modem.vhd" 103 -1 0 } } { "Modem.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Modem.vhd" 105 -1 0 } } { "Rxcver.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Rxcver.vhd" 117 -1 0 } } { "Modem.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Modem.vhd" 104 -1 0 } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 353 -1 0 } } { "Intface.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Intface.vhd" 352 -1 0 } } { "Txmitt.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Txmitt.vhd" 122 -1 0 } } { "Txmitt.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Txmitt.vhd" 123 -1 0 } } { "Txmitt.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Txmitt.vhd" 113 -1 0 } } { "Txmitt.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Txmitt.vhd" 342 -1 0 } } { "Txmitt.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Txmitt.vhd" 342 -1 0 } } { "Txmitt.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Txmitt.vhd" 342 -1 0 } } { "Txmitt.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Txmitt.vhd" 342 -1 0 } } { "Txmitt.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Txmitt.vhd" 121 -1 0 } } { "Rxcver.vhd" "" { Text "D:/EDAtool/altera/Design_ok/UART_VHDL/Rxcver.vhd" 127 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "270 " "Info: Implemented 270 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "22 " "Info: Implemented 22 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "15 " "Info: Implemented 15 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "233 " "Info: Implemented 233 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 30 21:13:38 2008 " "Info: Processing ended: Sun Mar 30 21:13:38 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}