uart_top.fit.summary

URAT异步通信接口的VHDL描述

Fitter Status : Successful - Sun Mar 30 21:13:48 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : UART_top
Top-level Entity Name : Uart_top
Family : Cyclone II
Device : EP2C5T144C6
Timing Models : Final
Total logic elements : 213 / 4,608 ( 5 % )
Total registers : 124
Total pins : 37 / 89 ( 42 % )
Total virtual pins : 0
Total memory bits : 0 / 119,808 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 26 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )