uart_top.map.rpt

URAT异步通信接口的VHDL描述

+---------------------------------------------------+
; Source assignments for Intface:U1                 ;
+-------------------+-------+------+----------------+
; Assignment        ; Value ; From ; To             ;
+-------------------+-------+------+----------------+
; POWER_UP_LEVEL    ; Low   ; -    ; Int_State.int3 ;
; POWER_UP_LEVEL    ; Low   ; -    ; Int_State.int2 ;
; POWER_UP_LEVEL    ; Low   ; -    ; Int_State.int1 ;
; POWER_UP_LEVEL    ; Low   ; -    ; Int_State.int0 ;
; POWER_UP_LEVEL    ; High  ; -    ; Int_State.idle ;
; PRESERVE_REGISTER ; on    ; -    ; RbrRDn1_r      ;
+-------------------+-------+------+----------------+


+------------------------------------------------------------+
; Source assignments for Rxcver:U3                           ;
+-------------------+-------+------+-------------------------+
; Assignment        ; Value ; From ; To                      ;
+-------------------+-------+------+-------------------------+
; PRESERVE_REGISTER ; on    ; -    ; ParityErr_r             ;
; PRESERVE_REGISTER ; on    ; -    ; FrameErr_r              ;
; PRESERVE_REGISTER ; on    ; -    ; BreakInt_r              ;
; PRESERVE_REGISTER ; on    ; -    ; OverrunErr_r            ;
; PRESERVE_REGISTER ; on    ; -    ; RBR_r[0]                ;
; PRESERVE_REGISTER ; on    ; -    ; RBR_r[1]                ;
; PRESERVE_REGISTER ; on    ; -    ; RBR_r[2]                ;
; PRESERVE_REGISTER ; on    ; -    ; RBR_r[3]                ;
; PRESERVE_REGISTER ; on    ; -    ; RBR_r[4]                ;
; PRESERVE_REGISTER ; on    ; -    ; RBR_r[5]                ;
; PRESERVE_REGISTER ; on    ; -    ; RBR_r[6]                ;
; PRESERVE_REGISTER ; on    ; -    ; RBR_r[7]                ;
; POWER_UP_LEVEL    ; Low   ; -    ; Rx_State.stop           ;
; POWER_UP_LEVEL    ; Low   ; -    ; Rx_State.parity         ;
; POWER_UP_LEVEL    ; Low   ; -    ; Rx_State.shift          ;
; POWER_UP_LEVEL    ; High  ; -    ; Rx_State.idle           ;
; PRESERVE_REGISTER ; on    ; -    ; RxFrmErr                ;
; PRESERVE_REGISTER ; on    ; -    ; RxPrtyErr               ;
; PRESERVE_REGISTER ; on    ; -    ; NumDataBitReceived_r[0] ;
; PRESERVE_REGISTER ; on    ; -    ; NumDataBitReceived_r[1] ;
; PRESERVE_REGISTER ; on    ; -    ; NumDataBitReceived_r[2] ;
; PRESERVE_REGISTER ; on    ; -    ; NumDataBitReceived_r[3] ;
; PRESERVE_REGISTER ; on    ; -    ; RSR[0]                  ;
; PRESERVE_REGISTER ; on    ; -    ; RSR[1]                  ;
; PRESERVE_REGISTER ; on    ; -    ; RSR[2]                  ;
; PRESERVE_REGISTER ; on    ; -    ; RSR[3]                  ;
; PRESERVE_REGISTER ; on    ; -    ; RSR[4]                  ;
; PRESERVE_REGISTER ; on    ; -    ; RSR[5]                  ;
; PRESERVE_REGISTER ; on    ; -    ; RSR[6]                  ;
; PRESERVE_REGISTER ; on    ; -    ; RSR[7]                  ;
; PRESERVE_REGISTER ; on    ; -    ; RxIdle_r                ;
; PRESERVE_REGISTER ; on    ; -    ; RbrDataRDY              ;
; PRESERVE_REGISTER ; on    ; -    ; HuntOne_r               ;
; POWER_UP_LEVEL    ; Low   ; -    ; Hunt_r                  ;
; PRESERVE_REGISTER ; on    ; -    ; Hunt_r                  ;
+-------------------+-------+------+-------------------------+


+----------------------------------------------------------+
; Source assignments for Txmitt:U4                         ;
+-------------------+-------+------+-----------------------+
; Assignment        ; Value ; From ; To                    ;
+-------------------+-------+------+-----------------------+
; PRESERVE_REGISTER ; on    ; -    ; ThrEmpty              ;
; PRESERVE_REGISTER ; on    ; -    ; TsrEmpty              ;
; POWER_UP_LEVEL    ; Low   ; -    ; Tx_State.stop_halfbit ;
; POWER_UP_LEVEL    ; Low   ; -    ; Tx_State.stop_2bit    ;
; POWER_UP_LEVEL    ; Low   ; -    ; Tx_State.stop_1bit    ;
; POWER_UP_LEVEL    ; Low   ; -    ; Tx_State.parity       ;
; POWER_UP_LEVEL    ; Low   ; -    ; Tx_State.shift        ;
; POWER_UP_LEVEL    ; High  ; -    ; Tx_State.start        ;
; PRESERVE_REGISTER ; on    ; -    ; TxParity_r            ;
; PRESERVE_REGISTER ; on    ; -    ; TxOutput              ;
; PRESERVE_REGISTER ; on    ; -    ; TSR[0]                ;
; PRESERVE_REGISTER ; on    ; -    ; TSR[1]                ;
; PRESERVE_REGISTER ; on    ; -    ; TSR[2]                ;
; PRESERVE_REGISTER ; on    ; -    ; TSR[3]                ;
; PRESERVE_REGISTER ; on    ; -    ; TSR[4]                ;
; PRESERVE_REGISTER ; on    ; -    ; TSR[5]                ;
; PRESERVE_REGISTER ; on    ; -    ; TSR[6]                ;
; PRESERVE_REGISTER ; on    ; -    ; TSR[7]                ;
; PRESERVE_REGISTER ; on    ; -    ; TxCNT_r[0]            ;
; PRESERVE_REGISTER ; on    ; -    ; TxCNT_r[1]            ;
; PRESERVE_REGISTER ; on    ; -    ; TxCNT_r[2]            ;
+-------------------+-------+------+-----------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun Mar 30 21:13:32 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off UART_top -c UART_top
Info: Found 2 design units, including 1 entities, in source file UART_top.vhd
    Info: Found design unit 1: Uart_top-Uart_top_a
    Info: Found entity 1: Uart_top
Info: Elaborating entity "UART_top" for the top level hierarchy
Warning: Using design file Intface.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: Intface-Intface_a
    Info: Found entity 1: Intface
Info: Elaborating entity "Intface" for hierarchy "Intface:U1"
Warning (10631): VHDL Process Statement warning at Intface.vhd(398): inferring latch(es) for signal or variable "ADDR_s", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at Intface.vhd(411): inferring latch(es) for signal or variable "CS_r", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at Intface.vhd(411): inferred latch for "CS_r"
Info (10041): Verilog HDL or VHDL info at Intface.vhd(398): inferred latch for "ADDR_s[0]"
Info (10041): Verilog HDL or VHDL info at Intface.vhd(398): inferred latch for "ADDR_s[1]"
Info (10041): Verilog HDL or VHDL info at Intface.vhd(398): inferred latch for "ADDR_s[2]"
Warning: Using design file Modem.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: Modem-Modem_a
    Info: Found entity 1: Modem
Info: Elaborating entity "Modem" for hierarchy "Modem:U2"
Warning: Using design file Rxcver.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: Rxcver-Rxcver_a
    Info: Found entity 1: Rxcver
Info: Elaborating entity "Rxcver" for hierarchy "Rxcver:U3"
Warning: Using design file Txmitt.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: Txmitt-Txmitt_a
    Info: Found entity 1: Txmitt
Info: Elaborating entity "Txmitt" for hierarchy "Txmitt:U4"
Info: State machine "|Uart_top|Txmitt:U4|Tx_State" contains 6 states
Info: State machine "|Uart_top|Rxcver:U3|Rx_State" contains 4 states
Info: State machine "|Uart_top|Intface:U1|Int_State" contains 5 states
Info: Selected Auto state machine encoding method for state machine "|Uart_top|Txmitt:U4|Tx_State"
Info: Encoding result for state machine "|Uart_top|Txmitt:U4|Tx_State"
    Info: Completed encoding using 6 state bits
        Info: Encoded state bit "Txmitt:U4|Tx_State.stop_halfbit"
        Info: Encoded state bit "Txmitt:U4|Tx_State.stop_2bit"
        Info: Encoded state bit "Txmitt:U4|Tx_State.stop_1bit"
        Info: Encoded state bit "Txmitt:U4|Tx_State.parity"
        Info: Encoded state bit "Txmitt:U4|Tx_State.shift"
        Info: Encoded state bit "Txmitt:U4|Tx_State.start"
    Info: State "|Uart_top|Txmitt:U4|Tx_State.start" uses code string "000000"
    Info: State "|Uart_top|Txmitt:U4|Tx_State.shift" uses code string "000011"
    Info: State "|Uart_top|Txmitt:U4|Tx_State.parity" uses code string "000101"
    Info: State "|Uart_top|Txmitt:U4|Tx_State.stop_1bit" uses code string "001001"
    Info: State "|Uart_top|Txmitt:U4|Tx_State.stop_2bit" uses code string "010001"
    Info: State "|Uart_top|Txmitt:U4|Tx_State.stop_halfbit" uses code string "100001"
Info: Selected Auto state machine encoding method for state machine "|Uart_top|Rxcver:U3|Rx_State"
Info: Encoding result for state machine "|Uart_top|Rxcver:U3|Rx_State"
    Info: Completed encoding using 4 state bits
        Info: Encoded state bit "Rxcver:U3|Rx_State.stop"
        Info: Encoded state bit "Rxcver:U3|Rx_State.parity"
        Info: Encoded state bit "Rxcver:U3|Rx_State.shift"
        Info: Encoded state bit "Rxcver:U3|Rx_State.idle"
    Info: State "|Uart_top|Rxcver:U3|Rx_State.idle" uses code string "0000"
    Info: State "|Uart_top|Rxcver:U3|Rx_State.shift" uses code string "0011"
    Info: State "|Uart_top|Rxcver:U3|Rx_State.parity" uses code string "0101"
    Info: State "|Uart_top|Rxcver:U3|Rx_State.stop" uses code string "1001"
Info: Selected Auto state machine encoding method for state machine "|Uart_top|Intface:U1|Int_State"
Info: Encoding result for state machine "|Uart_top|Intface:U1|Int_State"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "Intface:U1|Int_State.int3"
        Info: Encoded state bit "Intface:U1|Int_State.int2"
        Info: Encoded state bit "Intface:U1|Int_State.int1"
        Info: Encoded state bit "Intface:U1|Int_State.int0"
        Info: Encoded state bit "Intface:U1|Int_State.idle"
    Info: State "|Uart_top|Intface:U1|Int_State.idle" uses code string "00000"
    Info: State "|Uart_top|Intface:U1|Int_State.int0" uses code string "00011"
    Info: State "|Uart_top|Intface:U1|Int_State.int1" uses code string "00101"
    Info: State "|Uart_top|Intface:U1|Int_State.int2" uses code string "01001"
    Info: State "|Uart_top|Intface:U1|Int_State.int3" uses code string "10001"
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Implemented 270 device resources after synthesis - the final resource count might be different
    Info: Implemented 22 input pins
    Info: Implemented 15 output pins
    Info: Implemented 233 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings
    Info: Processing ended: Sun Mar 30 21:13:38 2008
    Info: Elapsed time: 00:00:07