uart_top.tan.summary

URAT异步通信接口的VHDL描述

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 6.578 ns
From           : SIN
To             : Rxcver:U3|RxPrtyErr
From Clock     : --
To Clock       : MCLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 10.713 ns
From           : Intface:U1|ADDR_s[1]
To             : DOUT[2]
From Clock     : ADSn
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 12.638 ns
From           : RDn
To             : DOUT[6]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 0.096 ns
From           : MR
To             : Intface:U1|RbrRDn1_r
From Clock     : --
To Clock       : MCLK
Failed Paths   : 0

Type           : Clock Setup: 'MCLK'
Slack          : N/A
Required Time  : None
Actual Time    : 272.26 MHz ( period = 3.673 ns )
From           : Rxcver:U3|RbrDataRDY
To             : Intface:U1|Int_State.int1
From Clock     : MCLK
To Clock       : MCLK
Failed Paths   : 0

Type           : Clock Hold: 'ADSn'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : Intface:U1|ADDR_s[2]
To             : Intface:U1|LCR[3]
From Clock     : ADSn
To Clock       : ADSn
Failed Paths   : 63

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 63

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