sin_wave.fit.rpt

来自「sin波形信号发生起的程序 VHDL语言描述 QUartus」· RPT 代码 · 共 735 行 · 第 1/5 页

; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Active Serial            ;
; Error detection CRC                          ; Off                      ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+----------------------------+
; Advanced Data - General    ;
+--------------------+-------+
; Name               ; Value ;
+--------------------+-------+
; Status Code        ; 0     ;
; Desired User Slack ; 0     ;
; Fit Attempts       ; 1     ;
+--------------------+-------+


+-----------------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                                         ;
+--------------------------------------------------------------------------------+--------------+
; Name                                                                           ; Value        ;
+--------------------------------------------------------------------------------+--------------+
; Auto Fit Point 1 - Fit Attempt 1                                               ; ff           ;
; Mid Wire Use - Fit Attempt 1                                                   ; 7            ;
; Mid Slack - Fit Attempt 1                                                      ; -4953        ;
; Internal Atom Count - Fit Attempt 1                                            ; 498          ;
; LE/ALM Count - Fit Attempt 1                                                   ; 498          ;
; LAB Count - Fit Attempt 1                                                      ; 51           ;
; Outputs per Lab - Fit Attempt 1                                                ; 3.706        ;
; Inputs per LAB - Fit Attempt 1                                                 ; 10.549       ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 0.118        ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:49;1:2     ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:48;1:3     ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:48;1:1;2:2 ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:48;1:1;2:2 ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:48;2:1;3:2 ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:48;2:1;3:2 ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:51         ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:49;1:2     ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:48;1:1;2:2 ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:48;2:1;3:2 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:48;1:2;2:1 ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:49;1:2     ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:48;1:1;2:2 ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:51         ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 0:1;1:50     ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:49;1:2     ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:51         ;
; LEs in Chains - Fit Attempt 1                                                  ; 21           ;
; LEs in Long Chains - Fit Attempt 1                                             ; 11           ;
; LABs with Chains - Fit Attempt 1                                               ; 3            ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0            ;
; Time - Fit Attempt 1                                                           ; 0            ;
; Time in tsm_tan.dll - Fit Attempt 1                                            ; 0.031        ;
+--------------------------------------------------------------------------------+--------------+


+---------------------------------------------+
; Advanced Data - Placement                   ;
+-------------------------------------+-------+
; Name                                ; Value ;
+-------------------------------------+-------+
; Auto Fit Point 2 - Fit Attempt 1    ; ff    ;
; Early Wire Use - Fit Attempt 1      ; 2     ;
; Early Slack - Fit Attempt 1         ; -4871 ;
; Auto Fit Point 3 - Fit Attempt 1    ; ff    ;
; Auto Fit Point 4 - Fit Attempt 1    ; ff    ;
; Mid Wire Use - Fit Attempt 1        ; 3     ;
; Mid Slack - Fit Attempt 1           ; -4175 ;
; Late Wire Use - Fit Attempt 1       ; 4     ;
; Late Slack - Fit Attempt 1          ; -4175 ;
; Auto Fit Point 5 - Fit Attempt 1    ; ff    ;
; Time - Fit Attempt 1                ; 0     ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.250 ;
+-------------------------------------+-------+


+---------------------------------------------+
; Advanced Data - Routing                     ;
+-------------------------------------+-------+
; Name                                ; Value ;
+-------------------------------------+-------+
; Early Slack - Fit Attempt 1         ; -2769 ;
; Early Wire Use - Fit Attempt 1      ; 3     ;
; Peak Regional Wire - Fit Attempt 1  ; 5     ;
; Mid Slack - Fit Attempt 1           ; -3593 ;
; Late Slack - Fit Attempt 1          ; -3351 ;
; Late Slack - Fit Attempt 1          ; -3351 ;
; Late Wire Use - Fit Attempt 1       ; 4     ;
; Time - Fit Attempt 1                ; 2     ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.892 ;
+-------------------------------------+-------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun Mar 30 15:14:55 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off sin_wave -c sin_wave
Info: Automatically selected device EP1C3T100C6 for design sin_wave
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: No exact pin location assignment(s) for 14 pins of 14 total pins
    Info: Pin wave_out[0] not assigned to an exact location on the device
    Info: Pin wave_out[1] not assigned to an exact location on the device
    Info: Pin wave_out[2] not assigned to an exact location on the device
    Info: Pin wave_out[3] not assigned to an exact location on the device
    Info: Pin wave_out[4] not assigned to an exact location on the device
    Info: Pin wave_out[5] not assigned to an exact location on the device
    Info: Pin wave_out[6] not assigned to an exact location on the device
    Info: Pin wave_out[7] not assigned to an exact location on the device
    Info: Pin wave_out[8] not assigned to an exact location on the device
    Info: Pin wave_out[9] not assigned to an exact location on the device
    Info: Pin wave_out[10] not assigned to an exact location on the device
    Info: Pin enable not assigned to an exact location on the device
    Info: Pin clock not assigned to an exact location on the device
    Info: Pin reset not assigned to an exact location on the device
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Automatically promoted signal "clock" to use Global clock in PIN 10
Info: Automatically promoted signal "reset" to use Global clock in PIN 66
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing: elapsed time is 00:00:01
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 12 (unused VREF, 3.30 VCCIO, 1 input, 11 output, 0 bidirectional)
        Info: I/O standards used: LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  11 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  16 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time