sin_wave.fit.qmsg

sin波形信号发生起的程序 VHDL语言描述 QUartus

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:01 " "Info: Finished register packing: elapsed time is 00:00:01" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "12 unused 3.30 1 11 0 " "Info: Number of I/O pins in group: 12 (unused VREF, 3.30 VCCIO, 1 input, 11 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 3 11 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  11 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 17 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 1 16 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  16 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 17 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.724 ns register register " "Info: Estimated most critical path is register to register delay of 3.724 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns table_index\[5\] 1 REG LAB_X18_Y9 124 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X18_Y9; Fanout = 124; REG Node = 'table_index\[5\]'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { table_index[5] } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.655 ns) + CELL(0.088 ns) 0.743 ns Equal0~110 2 COMB LAB_X19_Y9 4 " "Info: 2: + IC(0.655 ns) + CELL(0.088 ns) = 0.743 ns; Loc. = LAB_X19_Y9; Fanout = 4; COMB Node = 'Equal0~110'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.743 ns" { table_index[5] Equal0~110 } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.415 ns) + CELL(0.088 ns) 1.246 ns Equal0~111 3 COMB LAB_X19_Y9 2 " "Info: 3: + IC(0.415 ns) + CELL(0.088 ns) = 1.246 ns; Loc. = LAB_X19_Y9; Fanout = 2; COMB Node = 'Equal0~111'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.503 ns" { Equal0~110 Equal0~111 } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.456 ns) + CELL(0.088 ns) 1.790 ns Selector0~52 4 COMB LAB_X19_Y9 24 " "Info: 4: + IC(0.456 ns) + CELL(0.088 ns) = 1.790 ns; Loc. = LAB_X19_Y9; Fanout = 24; COMB Node = 'Selector0~52'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.544 ns" { Equal0~111 Selector0~52 } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.477 ns) + CELL(0.443 ns) 2.710 ns table_index\[1\]~591COUT1_599 5 COMB LAB_X18_Y9 2 " "Info: 5: + IC(0.477 ns) + CELL(0.443 ns) = 2.710 ns; Loc. = LAB_X18_Y9; Fanout = 2; COMB Node = 'table_index\[1\]~591COUT1_599'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.920 ns" { Selector0~52 table_index[1]~591COUT1_599 } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 2.772 ns table_index\[2\]~590COUT1_600 6 COMB LAB_X18_Y9 2 " "Info: 6: + IC(0.000 ns) + CELL(0.062 ns) = 2.772 ns; Loc. = LAB_X18_Y9; Fanout = 2; COMB Node = 'table_index\[2\]~590COUT1_600'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.062 ns" { table_index[1]~591COUT1_599 table_index[2]~590COUT1_600 } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 2.834 ns table_index\[3\]~589COUT1_601 7 COMB LAB_X18_Y9 2 " "Info: 7: + IC(0.000 ns) + CELL(0.062 ns) = 2.834 ns; Loc. = LAB_X18_Y9; Fanout = 2; COMB Node = 'table_index\[3\]~589COUT1_601'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.062 ns" { table_index[2]~590COUT1_600 table_index[3]~589COUT1_601 } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.199 ns) 3.033 ns table_index\[4\]~587 8 COMB LAB_X18_Y9 5 " "Info: 8: + IC(0.000 ns) + CELL(0.199 ns) = 3.033 ns; Loc. = LAB_X18_Y9; Fanout = 5; COMB Node = 'table_index\[4\]~587'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.199 ns" { table_index[3]~589COUT1_601 table_index[4]~587 } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.691 ns) 3.724 ns table_index\[7\] 9 REG LAB_X18_Y9 64 " "Info: 9: + IC(0.000 ns) + CELL(0.691 ns) = 3.724 ns; Loc. = LAB_X18_Y9; Fanout = 64; REG Node = 'table_index\[7\]'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.691 ns" { table_index[4]~587 table_index[7] } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.721 ns ( 46.21 % ) " "Info: Total cell delay = 1.721 ns ( 46.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.003 ns ( 53.79 % ) " "Info: Total interconnect delay = 2.003 ns ( 53.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.724 ns" { table_index[5] Equal0~110 Equal0~111 Selector0~52 table_index[1]~591COUT1_599 table_index[2]~590COUT1_600 table_index[3]~589COUT1_601 table_index[4]~587 table_index[7] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "2 5 " "Info: Average interconnect usage is 2% of the available device resources. Peak interconnect usage is 5%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x14_y0 x27_y14 " "Info: The peak interconnect region extends from location x14_y0 to location x27_y14" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Info: Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 30 15:15:02 2008 " "Info: Processing ended: Sun Mar 30 15:15:02 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.fit.smsg " "Info: Generated suppressed messages file D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}