sin_wave.map.qmsg

sin波形信号发生起的程序 VHDL语言描述 QUartus

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 30 15:14:30 2008 " "Info: Processing started: Sun Mar 30 15:14:30 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sin_wave -c sin_wave " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sin_wave -c sin_wave" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../quartus6.0/libraries/work/butter_lib.vhd 1 0 " "Info: Found 1 design units, including 0 entities, in source file ../../quartus6.0/libraries/work/butter_lib.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 butter_lib " "Info: Found design unit 1: butter_lib" {  } { { "../../quartus6.0/libraries/work/butter_lib.vhd" "" { Text "D:/EDAtool/altera/quartus6.0/libraries/work/butter_lib.vhd" 7 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../quartus6.0/libraries/work/sine_package.vhd 2 0 " "Info: Found 2 design units, including 0 entities, in source file ../../quartus6.0/libraries/work/sine_package.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sine_package " "Info: Found design unit 1: sine_package" {  } { { "../../quartus6.0/libraries/work/sine_package.vhd" "" { Text "D:/EDAtool/altera/quartus6.0/libraries/work/sine_package.vhd" 4 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sine_package-body " "Info: Found design unit 2: sine_package-body" {  } { { "../../quartus6.0/libraries/work/sine_package.vhd" "" { Text "D:/EDAtool/altera/quartus6.0/libraries/work/sine_package.vhd" 18 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "sin_wave.vhd 2 1 " "Warning: Using design file sin_wave.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sin_wave-arch1 " "Info: Found design unit 1: sin_wave-arch1" {  } { { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sin_wave " "Info: Found entity 1: sin_wave" {  } { { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "sin_wave " "Info: Elaborating entity \"sin_wave\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|sin_wave\|state 4 " "Info: State machine \"\|sin_wave\|state\" contains 4 states" {  } { { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 17 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|sin_wave\|state " "Info: Selected Auto state machine encoding method for state machine \"\|sin_wave\|state\"" {  } { { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 17 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|sin_wave\|state " "Info: Encoding result for state machine \"\|sin_wave\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "4 " "Info: Completed encoding using 4 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.change_up " "Info: Encoded state bit \"state.change_up\"" {  } { { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 24 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.counting_down " "Info: Encoded state bit \"state.counting_down\"" {  } { { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 24 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.change_down " "Info: Encoded state bit \"state.change_down\"" {  } { { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 24 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.counting_up " "Info: Encoded state bit \"state.counting_up\"" {  } { { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 24 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|sin_wave\|state.counting_up 0000 " "Info: State \"\|sin_wave\|state.counting_up\" uses code string \"0000\"" {  } { { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 24 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|sin_wave\|state.change_down 0011 " "Info: State \"\|sin_wave\|state.change_down\" uses code string \"0011\"" {  } { { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 24 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|sin_wave\|state.counting_down 0101 " "Info: State \"\|sin_wave\|state.counting_down\" uses code string \"0101\"" {  } { { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 24 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|sin_wave\|state.change_up 1001 " "Info: State \"\|sin_wave\|state.change_up\" uses code string \"1001\"" {  } { { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 24 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 17 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "514 " "Info: Implemented 514 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "11 " "Info: Implemented 11 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "500 " "Info: Implemented 500 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 30 15:14:53 2008 " "Info: Processing ended: Sun Mar 30 15:14:53 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:24 " "Info: Elapsed time: 00:00:24" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}