sin_wave.hier_info

sin波形信号发生起的程序 VHDL语言描述 QUartus

|sin_wave
clock => positive_cycle.CLK
clock => table_index[0].CLK
clock => table_index[1].CLK
clock => table_index[2].CLK
clock => table_index[3].CLK
clock => table_index[4].CLK
clock => table_index[5].CLK
clock => table_index[6].CLK
clock => table_index[7].CLK
clock => table_index[8].CLK
clock => table_index[9].CLK
clock => state~4.IN1
reset => positive_cycle.PRESET
reset => table_index[0].ACLR
reset => table_index[1].ACLR
reset => table_index[2].ACLR
reset => table_index[3].ACLR
reset => table_index[4].ACLR
reset => table_index[5].ACLR
reset => table_index[6].ACLR
reset => table_index[7].ACLR
reset => table_index[8].ACLR
reset => table_index[9].ACLR
reset => state~5.IN1
enable => state~0.OUTPUTSELECT
enable => state~1.OUTPUTSELECT
enable => state~2.OUTPUTSELECT
enable => state~3.OUTPUTSELECT
enable => table_index[2].ENA
enable => table_index[1].ENA
enable => table_index[0].ENA
enable => table_index[3].ENA
enable => table_index[4].ENA
enable => table_index[5].ENA
enable => table_index[6].ENA
enable => table_index[7].ENA
enable => table_index[8].ENA
enable => table_index[9].ENA
wave_out[0] <= wave_out~10.DB_MAX_OUTPUT_PORT_TYPE
wave_out[1] <= wave_out~9.DB_MAX_OUTPUT_PORT_TYPE
wave_out[2] <= wave_out~8.DB_MAX_OUTPUT_PORT_TYPE
wave_out[3] <= wave_out~7.DB_MAX_OUTPUT_PORT_TYPE
wave_out[4] <= wave_out~6.DB_MAX_OUTPUT_PORT_TYPE
wave_out[5] <= wave_out~5.DB_MAX_OUTPUT_PORT_TYPE
wave_out[6] <= wave_out~4.DB_MAX_OUTPUT_PORT_TYPE
wave_out[7] <= wave_out~3.DB_MAX_OUTPUT_PORT_TYPE
wave_out[8] <= wave_out~2.DB_MAX_OUTPUT_PORT_TYPE
wave_out[9] <= wave_out~1.DB_MAX_OUTPUT_PORT_TYPE
wave_out[10] <= wave_out~0.DB_MAX_OUTPUT_PORT_TYPE