📄 sin_wave.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register table_index\[9\] register table_index\[7\] 243.25 MHz 4.111 ns Internal " "Info: Clock \"clock\" has Internal fmax of 243.25 MHz between source register \"table_index\[9\]\" and destination register \"table_index\[7\]\" (period= 4.111 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.909 ns + Longest register register " "Info: + Longest register to register delay is 3.909 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns table_index\[9\] 1 REG LC_X18_Y9_N9 69 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X18_Y9_N9; Fanout = 69; REG Node = 'table_index\[9\]'" { } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { table_index[9] } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.699 ns) + CELL(0.340 ns) 1.039 ns Equal1~60 2 COMB LC_X17_Y9_N3 2 " "Info: 2: + IC(0.699 ns) + CELL(0.340 ns) = 1.039 ns; Loc. = LC_X17_Y9_N3; Fanout = 2; COMB Node = 'Equal1~60'" { } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.039 ns" { table_index[9] Equal1~60 } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 44 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.861 ns) + CELL(0.088 ns) 1.988 ns Equal1~62 3 COMB LC_X19_Y9_N5 4 " "Info: 3: + IC(0.861 ns) + CELL(0.088 ns) = 1.988 ns; Loc. = LC_X19_Y9_N5; Fanout = 4; COMB Node = 'Equal1~62'" { } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.949 ns" { Equal1~60 Equal1~62 } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 44 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.330 ns) + CELL(0.340 ns) 2.658 ns table_index\[0\]~596 4 COMB LC_X19_Y9_N1 10 " "Info: 4: + IC(0.330 ns) + CELL(0.340 ns) = 2.658 ns; Loc. = LC_X19_Y9_N1; Fanout = 10; COMB Node = 'table_index\[0\]~596'" { } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.670 ns" { Equal1~62 table_index[0]~596 } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.584 ns) + CELL(0.667 ns) 3.909 ns table_index\[7\] 5 REG LC_X18_Y9_N7 64 " "Info: 5: + IC(0.584 ns) + CELL(0.667 ns) = 3.909 ns; Loc. = LC_X18_Y9_N7; Fanout = 64; REG Node = 'table_index\[7\]'" { } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.251 ns" { table_index[0]~596 table_index[7] } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.435 ns ( 36.71 % ) " "Info: Total cell delay = 1.435 ns ( 36.71 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.474 ns ( 63.29 % ) " "Info: Total interconnect delay = 2.474 ns ( 63.29 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.909 ns" { table_index[9] Equal1~60 Equal1~62 table_index[0]~596 table_index[7] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "3.909 ns" { table_index[9] Equal1~60 Equal1~62 table_index[0]~596 table_index[7] } { 0.000ns 0.699ns 0.861ns 0.330ns 0.584ns } { 0.000ns 0.340ns 0.088ns 0.340ns 0.667ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.140 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 2.140 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clock 1 CLK PIN_10 15 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 15; CLK Node = 'clock'" { } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.463 ns) + CELL(0.547 ns) 2.140 ns table_index\[7\] 2 REG LC_X18_Y9_N7 64 " "Info: 2: + IC(0.463 ns) + CELL(0.547 ns) = 2.140 ns; Loc. = LC_X18_Y9_N7; Fanout = 64; REG Node = 'table_index\[7\]'" { } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.010 ns" { clock table_index[7] } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.36 % ) " "Info: Total cell delay = 1.677 ns ( 78.36 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.463 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.463 ns ( 21.64 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.140 ns" { clock table_index[7] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "2.140 ns" { clock clock~out0 table_index[7] } { 0.000ns 0.000ns 0.463ns } { 0.000ns 1.130ns 0.547ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.140 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 2.140 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clock 1 CLK PIN_10 15 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 15; CLK Node = 'clock'" { } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.463 ns) + CELL(0.547 ns) 2.140 ns table_index\[9\] 2 REG LC_X18_Y9_N9 69 " "Info: 2: + IC(0.463 ns) + CELL(0.547 ns) = 2.140 ns; Loc. = LC_X18_Y9_N9; Fanout = 69; REG Node = 'table_index\[9\]'" { } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.010 ns" { clock table_index[9] } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.36 % ) " "Info: Total cell delay = 1.677 ns ( 78.36 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.463 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.463 ns ( 21.64 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.140 ns" { clock table_index[9] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "2.140 ns" { clock clock~out0 table_index[9] } { 0.000ns 0.000ns 0.463ns } { 0.000ns 1.130ns 0.547ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.140 ns" { clock table_index[7] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "2.140 ns" { clock clock~out0 table_index[7] } { 0.000ns 0.000ns 0.463ns } { 0.000ns 1.130ns 0.547ns } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.140 ns" { clock table_index[9] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "2.140 ns" { clock clock~out0 table_index[9] } { 0.000ns 0.000ns 0.463ns } { 0.000ns 1.130ns 0.547ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" { } { { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 54 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" { } { { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 54 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.909 ns" { table_index[9] Equal1~60 Equal1~62 table_index[0]~596 table_index[7] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "3.909 ns" { table_index[9] Equal1~60 Equal1~62 table_index[0]~596 table_index[7] } { 0.000ns 0.699ns 0.861ns 0.330ns 0.584ns } { 0.000ns 0.340ns 0.088ns 0.340ns 0.667ns } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.140 ns" { clock table_index[7] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "2.140 ns" { clock clock~out0 table_index[7] } { 0.000ns 0.000ns 0.463ns } { 0.000ns 1.130ns 0.547ns } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.140 ns" { clock table_index[9] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "2.140 ns" { clock clock~out0 table_index[9] } { 0.000ns 0.000ns 0.463ns } { 0.000ns 1.130ns 0.547ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "table_index\[7\] enable clock 4.621 ns register " "Info: tsu for register \"table_index\[7\]\" (data pin = \"enable\", clock pin = \"clock\") is 4.621 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.732 ns + Longest pin register " "Info: + Longest pin to register delay is 6.732 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns enable 1 PIN PIN_69 6 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_69; Fanout = 6; PIN Node = 'enable'" { } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { enable } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.126 ns) + CELL(0.225 ns) 5.481 ns table_index\[0\]~596 2 COMB LC_X19_Y9_N1 10 " "Info: 2: + IC(4.126 ns) + CELL(0.225 ns) = 5.481 ns; Loc. = LC_X19_Y9_N1; Fanout = 10; COMB Node = 'table_index\[0\]~596'" { } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "4.351 ns" { enable table_index[0]~596 } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.584 ns) + CELL(0.667 ns) 6.732 ns table_index\[7\] 3 REG LC_X18_Y9_N7 64 " "Info: 3: + IC(0.584 ns) + CELL(0.667 ns) = 6.732 ns; Loc. = LC_X18_Y9_N7; Fanout = 64; REG Node = 'table_index\[7\]'" { } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.251 ns" { table_index[0]~596 table_index[7] } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.022 ns ( 30.04 % ) " "Info: Total cell delay = 2.022 ns ( 30.04 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.710 ns ( 69.96 % ) " "Info: Total interconnect delay = 4.710 ns ( 69.96 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "6.732 ns" { enable table_index[0]~596 table_index[7] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "6.732 ns" { enable enable~out0 table_index[0]~596 table_index[7] } { 0.000ns 0.000ns 4.126ns 0.584ns } { 0.000ns 1.130ns 0.225ns 0.667ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" { } { { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 54 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.140 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 2.140 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clock 1 CLK PIN_10 15 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 15; CLK Node = 'clock'" { } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.463 ns) + CELL(0.547 ns) 2.140 ns table_index\[7\] 2 REG LC_X18_Y9_N7 64 " "Info: 2: + IC(0.463 ns) + CELL(0.547 ns) = 2.140 ns; Loc. = LC_X18_Y9_N7; Fanout = 64; REG Node = 'table_index\[7\]'" { } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.010 ns" { clock table_index[7] } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.36 % ) " "Info: Total cell delay = 1.677 ns ( 78.36 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.463 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.463 ns ( 21.64 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.140 ns" { clock table_index[7] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "2.140 ns" { clock clock~out0 table_index[7] } { 0.000ns 0.000ns 0.463ns } { 0.000ns 1.130ns 0.547ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "6.732 ns" { enable table_index[0]~596 table_index[7] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "6.732 ns" { enable enable~out0 table_index[0]~596 table_index[7] } { 0.000ns 0.000ns 4.126ns 0.584ns } { 0.000ns 1.130ns 0.225ns 0.667ns } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.140 ns" { clock table_index[7] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "2.140 ns" { clock clock~out0 table_index[7] } { 0.000ns 0.000ns 0.463ns } { 0.000ns 1.130ns 0.547ns } } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock wave_out\[10\] table_index\[1\] 16.186 ns register " "Info: tco from clock \"clock\" to destination pin \"wave_out\[10\]\" through register \"table_index\[1\]\" is 16.186 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.140 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 2.140 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clock 1 CLK PIN_10 15 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 15; CLK Node = 'clock'" { } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.463 ns) + CELL(0.547 ns) 2.140 ns table_index\[1\] 2 REG LC_X18_Y9_N1 162 " "Info: 2: + IC(0.463 ns) + CELL(0.547 ns) = 2.140 ns; Loc. = LC_X18_Y9_N1; Fanout = 162; REG Node = 'table_index\[1\]'" { } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.010 ns" { clock table_index[1] } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.36 % ) " "Info: Total cell delay = 1.677 ns ( 78.36 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.463 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.463 ns ( 21.64 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.140 ns" { clock table_index[1] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "2.140 ns" { clock clock~out0 table_index[1] } { 0.000ns 0.000ns 0.463ns } { 0.000ns 1.130ns 0.547ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" { } { { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 54 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.873 ns + Longest register pin " "Info: + Longest register to pin delay is 13.873 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns table_index\[1\] 1 REG LC_X18_Y9_N1 162 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X18_Y9_N1; Fanout = 162; REG Node = 'table_index\[1\]'" { } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { table_index[1] } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.489 ns) + CELL(0.454 ns) 2.943 ns Ram0~20642 2 COMB LC_X20_Y6_N6 2 " "Info: 2: + IC(2.489 ns) + CELL(0.454 ns) = 2.943 ns; Loc. = LC_X20_Y6_N6; Fanout = 2; COMB Node = 'Ram0~20642'" { } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.943 ns" { table_index[1] Ram0~20642 } "NODE_NAME" } } { "../../quartus6.0/libraries/work/sine_package.vhd" "" { Text "D:/EDAtool/altera/quartus6.0/libraries/work/sine_package.vhd" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.957 ns) + CELL(0.454 ns) 4.354 ns Ram0~20645 3 COMB LC_X19_Y5_N8 1 " "Info: 3: + IC(0.957 ns) + CELL(0.454 ns) = 4.354 ns; Loc. = LC_X19_Y5_N8; Fanout = 1; COMB Node = 'Ram0~20645'" { } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.411 ns" { Ram0~20642 Ram0~20645 } "NODE_NAME" } } { "../../quartus6.0/libraries/work/sine_package.vhd" "" { Text "D:/EDAtool/altera/quartus6.0/libraries/work/sine_package.vhd" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.313 ns) + CELL(0.340 ns) 5.007 ns Ram0~20646 4 COMB LC_X19_Y5_N3 1 " "Info: 4: + IC(0.313 ns) + CELL(0.340 ns) = 5.007 ns; Loc. = LC_X19_Y5_N3; Fanout = 1; COMB Node = 'Ram0~20646'" { } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.653 ns" { Ram0~20645 Ram0~20646 } "NODE_NAME" } } { "../../quartus6.0/libraries/work/sine_package.vhd" "" { Text "D:/EDAtool/altera/quartus6.0/libraries/work/sine_package.vhd" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.329 ns) + CELL(0.088 ns) 5.424 ns Ram0~20647 5 COMB LC_X19_Y5_N6 1 " "Info: 5: + IC(0.329 ns) + CELL(0.088 ns) = 5.424 ns; Loc. = LC_X19_Y5_N6; Fanout = 1; COMB Node = 'Ram0~20647'" { } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.417 ns" { Ram0~20646 Ram0~20647 } "NODE_NAME" } } { "../../quartus6.0/libraries/work/sine_package.vhd" "" { Text "D:/EDAtool/altera/quartus6.0/libraries/work/sine_package.vhd" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.220 ns) + CELL(0.225 ns) 6.869 ns Ram0~20654 6 COMB LC_X17_Y9_N4 1 " "Info: 6: + IC(1.220 ns) + CELL(0.225 ns) = 6.869 ns; Loc. = LC_X17_Y9_N4; Fanout = 1; COMB Node = 'Ram0~20654'" { } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.445 ns" { Ram0~20647 Ram0~20654 } "NODE_NAME" } } { "../../quartus6.0/libraries/work/sine_package.vhd" "" { Text "D:/EDAtool/altera/quartus6.0/libraries/work/sine_package.vhd" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.950 ns) + CELL(0.088 ns) 7.907 ns Ram0~20675 7 COMB LC_X18_Y7_N1 1 " "Info: 7: + IC(0.950 ns) + CELL(0.088 ns) = 7.907 ns; Loc. = LC_X18_Y7_N1; Fanout = 1; COMB Node = 'Ram0~20675'" { } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.038 ns" { Ram0~20654 Ram0~20675 } "NODE_NAME" } } { "../../quartus6.0/libraries/work/sine_package.vhd" "" { Text "D:/EDAtool/altera/quartus6.0/libraries/work/sine_package.vhd" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.333 ns) + CELL(0.088 ns) 8.328 ns Ram0~20690 8 COMB LC_X18_Y7_N4 3 " "Info: 8: + IC(0.333 ns) + CELL(0.088 ns) = 8.328 ns; Loc. = LC_X18_Y7_N4; Fanout = 3; COMB Node = 'Ram0~20690'" { } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.421 ns" { Ram0~20675 Ram0~20690 } "NODE_NAME" } } { "../../quartus6.0/libraries/work/sine_package.vhd" "" { Text "D:/EDAtool/altera/quartus6.0/libraries/work/sine_package.vhd" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.178 ns) + CELL(0.326 ns) 9.832 ns Add2~277 9 COMB LC_X22_Y9_N8 2 " "Info: 9: + IC(1.178 ns) + CELL(0.326 ns) = 9.832 ns; Loc. = LC_X22_Y9_N8; Fanout = 2; COMB Node = 'Add2~277'" { } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.504 ns" { Ram0~20690 Add2~277 } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.209 ns) 10.041 ns Add2~279 10 COMB LC_X22_Y9_N9 6 " "Info: 10: + IC(0.000 ns) + CELL(0.209 ns) = 10.041 ns; Loc. = LC_X22_Y9_N9; Fanout = 6; COMB Node = 'Add2~279'" { } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.209 ns" { Add2~277 Add2~279 } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.105 ns) 10.146 ns Add2~289 11 COMB LC_X22_Y8_N4 1 " "Info: 11: + IC(0.000 ns) + CELL(0.105 ns) = 10.146 ns; Loc. = LC_X22_Y8_N4; Fanout = 1; COMB Node = 'Add2~289'" { } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.105 ns" { Add2~279 Add2~289 } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.478 ns) 10.624 ns Add2~290 12 COMB LC_X22_Y8_N5 1 " "Info: 12: + IC(0.000 ns) + CELL(0.478 ns) = 10.624 ns; Loc. = LC_X22_Y8_N5; Fanout = 1; COMB Node = 'Add2~290'" { } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.478 ns" { Add2~289 Add2~290 } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.615 ns) + CELL(1.634 ns) 13.873 ns wave_out\[10\] 13 PIN PIN_71 0 " "Info: 13: + IC(1.615 ns) + CELL(1.634 ns) = 13.873 ns; Loc. = PIN_71; Fanout = 0; PIN Node = 'wave_out\[10\]'" { } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.249 ns" { Add2~290 wave_out[10] } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.489 ns ( 32.36 % ) " "Info: Total cell delay = 4.489 ns ( 32.36 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.384 ns ( 67.64 % ) " "Info: Total interconnect delay = 9.384 ns ( 67.64 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "13.873 ns" { table_index[1] Ram0~20642 Ram0~20645 Ram0~20646 Ram0~20647 Ram0~20654 Ram0~20675 Ram0~20690 Add2~277 Add2~279 Add2~289 Add2~290 wave_out[10] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "13.873 ns" { table_index[1] Ram0~20642 Ram0~20645 Ram0~20646 Ram0~20647 Ram0~20654 Ram0~20675 Ram0~20690 Add2~277 Add2~279 Add2~289 Add2~290 wave_out[10] } { 0.000ns 2.489ns 0.957ns 0.313ns 0.329ns 1.220ns 0.950ns 0.333ns 1.178ns 0.000ns 0.000ns 0.000ns 1.615ns } { 0.000ns 0.454ns 0.454ns 0.340ns 0.088ns 0.225ns 0.088ns 0.088ns 0.326ns 0.209ns 0.105ns 0.478ns 1.634ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.140 ns" { clock table_index[1] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "2.140 ns" { clock clock~out0 table_index[1] } { 0.000ns 0.000ns 0.463ns } { 0.000ns 1.130ns 0.547ns } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "13.873 ns" { table_index[1] Ram0~20642 Ram0~20645 Ram0~20646 Ram0~20647 Ram0~20654 Ram0~20675 Ram0~20690 Add2~277 Add2~279 Add2~289 Add2~290 wave_out[10] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "13.873 ns" { table_index[1] Ram0~20642 Ram0~20645 Ram0~20646 Ram0~20647 Ram0~20654 Ram0~20675 Ram0~20690 Add2~277 Add2~279 Add2~289 Add2~290 wave_out[10] } { 0.000ns 2.489ns 0.957ns 0.313ns 0.329ns 1.220ns 0.950ns 0.333ns 1.178ns 0.000ns 0.000ns 0.000ns 1.615ns } { 0.000ns 0.454ns 0.454ns 0.340ns 0.088ns 0.225ns 0.088ns 0.088ns 0.326ns 0.209ns 0.105ns 0.478ns 1.634ns } } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "positive_cycle enable clock -3.664 ns register " "Info: th for register \"positive_cycle\" (data pin = \"enable\", clock pin = \"clock\") is -3.664 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.140 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 2.140 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clock 1 CLK PIN_10 15 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 15; CLK Node = 'clock'" { } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.463 ns) + CELL(0.547 ns) 2.140 ns positive_cycle 2 REG LC_X22_Y9_N1 31 " "Info: 2: + IC(0.463 ns) + CELL(0.547 ns) = 2.140 ns; Loc. = LC_X22_Y9_N1; Fanout = 31; REG Node = 'positive_cycle'" { } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.010 ns" { clock positive_cycle } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.36 % ) " "Info: Total cell delay = 1.677 ns ( 78.36 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.463 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.463 ns ( 21.64 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.140 ns" { clock positive_cycle } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "2.140 ns" { clock clock~out0 positive_cycle } { 0.000ns 0.000ns 0.463ns } { 0.000ns 1.130ns 0.547ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.012 ns + " "Info: + Micro hold delay of destination is 0.012 ns" { } { { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 19 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.816 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.816 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns enable 1 PIN PIN_69 6 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_69; Fanout = 6; PIN Node = 'enable'" { } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { enable } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.118 ns) + CELL(0.568 ns) 5.816 ns positive_cycle 2 REG LC_X22_Y9_N1 31 " "Info: 2: + IC(4.118 ns) + CELL(0.568 ns) = 5.816 ns; Loc. = LC_X22_Y9_N1; Fanout = 31; REG Node = 'positive_cycle'" { } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "4.686 ns" { enable positive_cycle } "NODE_NAME" } } { "sin_wave.vhd" "" { Text "D:/EDAtool/altera/Design_ok/Sinwave generator/sin_wave.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.698 ns ( 29.20 % ) " "Info: Total cell delay = 1.698 ns ( 29.20 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.118 ns ( 70.80 % ) " "Info: Total interconnect delay = 4.118 ns ( 70.80 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "5.816 ns" { enable positive_cycle } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "5.816 ns" { enable enable~out0 positive_cycle } { 0.000ns 0.000ns 4.118ns } { 0.000ns 1.130ns 0.568ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.140 ns" { clock positive_cycle } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "2.140 ns" { clock clock~out0 positive_cycle } { 0.000ns 0.000ns 0.463ns } { 0.000ns 1.130ns 0.547ns } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "5.816 ns" { enable positive_cycle } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "5.816 ns" { enable enable~out0 positive_cycle } { 0.000ns 0.000ns 4.118ns } { 0.000ns 1.130ns 0.568ns } } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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