sin_wave.tan.rpt

sin波形信号发生起的程序 VHDL语言描述 QUartus

; N/A   ; None         ; 14.296 ns  ; table_index[9] ; wave_out[3]  ; clock      ;
; N/A   ; None         ; 14.292 ns  ; table_index[4] ; wave_out[2]  ; clock      ;
; N/A   ; None         ; 14.252 ns  ; table_index[0] ; wave_out[3]  ; clock      ;
; N/A   ; None         ; 14.246 ns  ; table_index[5] ; wave_out[3]  ; clock      ;
; N/A   ; None         ; 14.227 ns  ; table_index[7] ; wave_out[3]  ; clock      ;
; N/A   ; None         ; 14.201 ns  ; table_index[6] ; wave_out[3]  ; clock      ;
; N/A   ; None         ; 14.189 ns  ; table_index[4] ; wave_out[3]  ; clock      ;
; N/A   ; None         ; 14.068 ns  ; table_index[0] ; wave_out[1]  ; clock      ;
; N/A   ; None         ; 14.062 ns  ; table_index[5] ; wave_out[1]  ; clock      ;
; N/A   ; None         ; 14.017 ns  ; table_index[6] ; wave_out[1]  ; clock      ;
; N/A   ; None         ; 13.887 ns  ; table_index[8] ; wave_out[0]  ; clock      ;
; N/A   ; None         ; 13.797 ns  ; table_index[3] ; wave_out[0]  ; clock      ;
; N/A   ; None         ; 13.743 ns  ; table_index[2] ; wave_out[0]  ; clock      ;
; N/A   ; None         ; 13.699 ns  ; table_index[9] ; wave_out[0]  ; clock      ;
; N/A   ; None         ; 13.630 ns  ; table_index[7] ; wave_out[0]  ; clock      ;
; N/A   ; None         ; 13.581 ns  ; table_index[4] ; wave_out[0]  ; clock      ;
; N/A   ; None         ; 13.560 ns  ; table_index[1] ; wave_out[0]  ; clock      ;
; N/A   ; None         ; 13.116 ns  ; table_index[6] ; wave_out[0]  ; clock      ;
; N/A   ; None         ; 9.323 ns   ; table_index[5] ; wave_out[0]  ; clock      ;
; N/A   ; None         ; 8.965 ns   ; table_index[0] ; wave_out[0]  ; clock      ;
; N/A   ; None         ; 7.856 ns   ; positive_cycle ; wave_out[10] ; clock      ;
; N/A   ; None         ; 7.688 ns   ; positive_cycle ; wave_out[5]  ; clock      ;
; N/A   ; None         ; 7.683 ns   ; positive_cycle ; wave_out[7]  ; clock      ;
; N/A   ; None         ; 7.467 ns   ; positive_cycle ; wave_out[8]  ; clock      ;
; N/A   ; None         ; 7.388 ns   ; positive_cycle ; wave_out[9]  ; clock      ;
; N/A   ; None         ; 7.359 ns   ; positive_cycle ; wave_out[6]  ; clock      ;
; N/A   ; None         ; 7.302 ns   ; positive_cycle ; wave_out[4]  ; clock      ;
; N/A   ; None         ; 7.214 ns   ; positive_cycle ; wave_out[1]  ; clock      ;
; N/A   ; None         ; 7.102 ns   ; positive_cycle ; wave_out[2]  ; clock      ;
; N/A   ; None         ; 6.999 ns   ; positive_cycle ; wave_out[3]  ; clock      ;
; N/A   ; None         ; 6.402 ns   ; positive_cycle ; wave_out[0]  ; clock      ;
+-------+--------------+------------+----------------+--------------+------------+


+-----------------------------------------------------------------------------------+
; th                                                                                ;
+---------------+-------------+-----------+--------+---------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To                  ; To Clock ;
+---------------+-------------+-----------+--------+---------------------+----------+
; N/A           ; None        ; -3.664 ns ; enable ; positive_cycle      ; clock    ;
; N/A           ; None        ; -3.793 ns ; enable ; state.counting_down ; clock    ;
; N/A           ; None        ; -3.793 ns ; enable ; state.change_down   ; clock    ;
; N/A           ; None        ; -3.793 ns ; enable ; state.counting_up   ; clock    ;
; N/A           ; None        ; -3.795 ns ; enable ; state.change_up     ; clock    ;
; N/A           ; None        ; -4.580 ns ; enable ; table_index[7]      ; clock    ;
; N/A           ; None        ; -4.580 ns ; enable ; table_index[9]      ; clock    ;
; N/A           ; None        ; -4.580 ns ; enable ; table_index[8]      ; clock    ;
; N/A           ; None        ; -4.580 ns ; enable ; table_index[4]      ; clock    ;
; N/A           ; None        ; -4.580 ns ; enable ; table_index[3]      ; clock    ;
; N/A           ; None        ; -4.580 ns ; enable ; table_index[2]      ; clock    ;
; N/A           ; None        ; -4.580 ns ; enable ; table_index[1]      ; clock    ;
; N/A           ; None        ; -4.580 ns ; enable ; table_index[0]      ; clock    ;
; N/A           ; None        ; -4.580 ns ; enable ; table_index[6]      ; clock    ;
; N/A           ; None        ; -4.580 ns ; enable ; table_index[5]      ; clock    ;
+---------------+-------------+-----------+--------+---------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun Mar 30 15:15:07 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off sin_wave -c sin_wave --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" has Internal fmax of 243.25 MHz between source register "table_index[9]" and destination register "table_index[7]" (period= 4.111 ns)
    Info: + Longest register to register delay is 3.909 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X18_Y9_N9; Fanout = 69; REG Node = 'table_index[9]'
        Info: 2: + IC(0.699 ns) + CELL(0.340 ns) = 1.039 ns; Loc. = LC_X17_Y9_N3; Fanout = 2; COMB Node = 'Equal1~60'
        Info: 3: + IC(0.861 ns) + CELL(0.088 ns) = 1.988 ns; Loc. = LC_X19_Y9_N5; Fanout = 4; COMB Node = 'Equal1~62'
        Info: 4: + IC(0.330 ns) + CELL(0.340 ns) = 2.658 ns; Loc. = LC_X19_Y9_N1; Fanout = 10; COMB Node = 'table_index[0]~596'
        Info: 5: + IC(0.584 ns) + CELL(0.667 ns) = 3.909 ns; Loc. = LC_X18_Y9_N7; Fanout = 64; REG Node = 'table_index[7]'
        Info: Total cell delay = 1.435 ns ( 36.71 % )
        Info: Total interconnect delay = 2.474 ns ( 63.29 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clock" to destination register is 2.140 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 15; CLK Node = 'clock'
            Info: 2: + IC(0.463 ns) + CELL(0.547 ns) = 2.140 ns; Loc. = LC_X18_Y9_N7; Fanout = 64; REG Node = 'table_index[7]'
            Info: Total cell delay = 1.677 ns ( 78.36 % )
            Info: Total interconnect delay = 0.463 ns ( 21.64 % )
        Info: - Longest clock path from clock "clock" to source register is 2.140 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 15; CLK Node = 'clock'
            Info: 2: + IC(0.463 ns) + CELL(0.547 ns) = 2.140 ns; Loc. = LC_X18_Y9_N9; Fanout = 69; REG Node = 'table_index[9]'
            Info: Total cell delay = 1.677 ns ( 78.36 % )
            Info: Total interconnect delay = 0.463 ns ( 21.64 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Micro setup delay of destination is 0.029 ns
Info: tsu for register "table_index[7]" (data pin = "enable", clock pin = "clock") is 4.621 ns
    Info: + Longest pin to register delay is 6.732 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_69; Fanout = 6; PIN Node = 'enable'
        Info: 2: + IC(4.126 ns) + CELL(0.225 ns) = 5.481 ns; Loc. = LC_X19_Y9_N1; Fanout = 10; COMB Node = 'table_index[0]~596'
        Info: 3: + IC(0.584 ns) + CELL(0.667 ns) = 6.732 ns; Loc. = LC_X18_Y9_N7; Fanout = 64; REG Node = 'table_index[7]'
        Info: Total cell delay = 2.022 ns ( 30.04 % )
        Info: Total interconnect delay = 4.710 ns ( 69.96 % )
    Info: + Micro setup delay of destination is 0.029 ns
    Info: - Shortest clock path from clock "clock" to destination register is 2.140 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 15; CLK Node = 'clock'
        Info: 2: + IC(0.463 ns) + CEL