sin_wave.map.rpt

sin波形信号发生起的程序 VHDL语言描述 QUartus

;                                             ;                ;
; Logic element usage by number of LUT inputs ;                ;
;     -- 4 input functions                    ; 404            ;
;     -- 3 input functions                    ; 78             ;
;     -- 2 input functions                    ; 14             ;
;     -- 1 input functions                    ; 1              ;
;     -- 0 input functions                    ; 0              ;
;         -- Combinational cells for routing  ; 0              ;
;                                             ;                ;
; Logic elements by mode                      ;                ;
;     -- normal mode                          ; 481            ;
;     -- arithmetic mode                      ; 19             ;
;     -- qfbk mode                            ; 0              ;
;     -- register cascade mode                ; 0              ;
;     -- synchronous clear/load mode          ; 0              ;
;     -- asynchronous clear/load mode         ; 15             ;
;                                             ;                ;
; Total registers                             ; 15             ;
; Total logic cells in carry chains           ; 21             ;
; I/O pins                                    ; 14             ;
; Maximum fan-out node                        ; table_index[8] ;
; Maximum fan-out                             ; 174            ;
; Total fan-out                               ; 1937           ;
; Average fan-out                             ; 3.77           ;
+---------------------------------------------+----------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                           ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |sin_wave                  ; 500 (500)   ; 15           ; 0           ; 0    ; 14   ; 0            ; 485 (485)    ; 3 (3)             ; 12 (12)          ; 21 (21)         ; 0 (0)      ; |sin_wave           ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-----------------------------------------------------------------------------------------------------+
; State Machine - |sin_wave|state                                                                     ;
+---------------------+-----------------+---------------------+-------------------+-------------------+
; Name                ; state.change_up ; state.counting_down ; state.change_down ; state.counting_up ;
+---------------------+-----------------+---------------------+-------------------+-------------------+
; state.counting_up   ; 0               ; 0                   ; 0                 ; 0                 ;
; state.change_down   ; 0               ; 0                   ; 1                 ; 1                 ;
; state.counting_down ; 0               ; 1                   ; 0                 ; 1                 ;
; state.change_up     ; 1               ; 0                   ; 0                 ; 1                 ;
+---------------------+-----------------+---------------------+-------------------+-------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 15    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 13    ;
; Number of registers using Asynchronous Load  ; 2     ;
; Number of registers using Clock Enable       ; 14    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; state.counting_up                      ; 2       ;
; Total number of inverted registers = 1 ;         ;
+----------------------------------------+---------+


+-----------------------------------------------------+
; Source assignments for Top-level Entity: |sin_wave  ;
+----------------+-------+------+---------------------+
; Assignment     ; Value ; From ; To                  ;
+----------------+-------+------+---------------------+
; POWER_UP_LEVEL ; Low   ; -    ; table_index[2]      ;
; POWER_UP_LEVEL ; Low   ; -    ; table_index[1]      ;
; POWER_UP_LEVEL ; Low   ; -    ; table_index[0]      ;
; POWER_UP_LEVEL ; Low   ; -    ; positive_cycle      ;
; POWER_UP_LEVEL ; Low   ; -    ; table_index[3]      ;
; POWER_UP_LEVEL ; Low   ; -    ; table_index[4]      ;
; POWER_UP_LEVEL ; Low   ; -    ; table_index[5]      ;
; POWER_UP_LEVEL ; Low   ; -    ; table_index[6]      ;
; POWER_UP_LEVEL ; Low   ; -    ; table_index[7]      ;
; POWER_UP_LEVEL ; Low   ; -    ; table_index[8]      ;
; POWER_UP_LEVEL ; Low   ; -    ; table_index[9]      ;
; POWER_UP_LEVEL ; Low   ; -    ; state.change_up     ;
; POWER_UP_LEVEL ; Low   ; -    ; state.counting_down ;
; POWER_UP_LEVEL ; Low   ; -    ; state.change_down   ;
; POWER_UP_LEVEL ; High  ; -    ; state.counting_up   ;
+----------------+-------+------+---------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun Mar 30 15:14:30 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sin_wave -c sin_wave
Info: Found 1 design units, including 0 entities, in source file ../../quartus6.0/libraries/work/butter_lib.vhd
    Info: Found design unit 1: butter_lib
Info: Found 2 design units, including 0 entities, in source file ../../quartus6.0/libraries/work/sine_package.vhd
    Info: Found design unit 1: sine_package
    Info: Found design unit 2: sine_package-body
Warning: Using design file sin_wave.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: sin_wave-arch1
    Info: Found entity 1: sin_wave
Info: Elaborating entity "sin_wave" for the top level hierarchy
Info: State machine "|sin_wave|state" contains 4 states
Info: Selected Auto state machine encoding method for state machine "|sin_wave|state"
Info: Encoding result for state machine "|sin_wave|state"
    Info: Completed encoding using 4 state bits
        Info: Encoded state bit "state.change_up"
        Info: Encoded state bit "state.counting_down"
        Info: Encoded state bit "state.change_down"
        Info: Encoded state bit "state.counting_up"
    Info: State "|sin_wave|state.counting_up" uses code string "0000"
    Info: State "|sin_wave|state.change_down" uses code string "0011"
    Info: State "|sin_wave|state.counting_down" uses code string "0101"
    Info: State "|sin_wave|state.change_up" uses code string "1001"
Info: Implemented 514 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 11 output pins
    Info: Implemented 500 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Processing ended: Sun Mar 30 15:14:53 2008
    Info: Elapsed time: 00:00:24