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<H1>Synthesisable Sine Wave Generator</H1>
<P>This page offers you a customisable sine wave generator. Below is a generic 
VHDL description of a sine wave generator. It is parameterised by constants and 
subtypes declared in <SPAN class=snippet>sine_package</SPAN>. </P>
<P>Further below is a HTML form for you to specify word and address sizes for a 
lookup table to store the values of a sine wave. Submit the form and a short 
Perl script runs on this server to generate a customised <SPAN 
class=snippet>sine_package</SPAN> complete with lookup table for you. </P>
<P>This implementation is moderately memory efficient because it stores only the 
first Pi/2 radians of sine values. The second Pi/2 radians is a mirror image of 
the first in time and the second Pi radians is a mirror image in amplitude of 
the first Pi radians. </P>
<P>Memory could be saved if the increments were recorded rather than each 
absolute value. Fewer bits per value would be needed, however, extra hardware 
would be needed for an adder. </P><PRE>-- Synthesisable design for a sine wave generator
-- Copyright Doulos Ltd
-- SD, 07 Aug 2003

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sine_package.all;

entity sine_wave is
  port( clock, reset, enable: in std_logic;
        wave_out: out sine_vector_type);
end;

architecture arch1 of sine_wave is
  type state_type is ( counting_up, change_down, counting_down, change_up );
  signal state, next_state: state_type;
  signal table_index: table_index_type;
  signal positive_cycle: boolean;
begin

  process( clock, reset )
  begin
    if reset = '1' then
      state &lt;= counting_up;
    elsif rising_edge( clock ) then
      if enable = '1' then
        state &lt;= next_state;
      end if;
    end if;
  end process;

  process( state, table_index )
  begin
    next_state &lt;= state;
    case state is
      when counting_up =&gt;
        if table_index = max_table_index then
          next_state &lt;= change_down;
        end if;
      when change_down =&gt;
        next_state &lt;= counting_down;
      when counting_down =&gt;
        if table_index = 0 then
          next_state &lt;= change_up;
        end if;
      when others =&gt; -- change_up
        next_state &lt;= counting_up;
    end case;
  end process;

  process( clock, reset )
  begin
    if reset = '1' then
      table_index &lt;= 0;
      positive_cycle &lt;= true;
    elsif rising_edge( clock ) then
      if enable = '1' then
        case next_state is
          when counting_up =&gt;
            table_index &lt;= table_index + 1;
          when counting_down =&gt;
            table_index &lt;= table_index - 1;
          when change_up =&gt;
            positive_cycle &lt;= not positive_cycle;
          when others =&gt;
            -- nothing to do
        end case;
      end if;
    end if;
  end process;

  process( table_index, positive_cycle )
    variable table_value: table_value_type;
  begin
    table_value := get_table_value( table_index );
    if positive_cycle then
      wave_out &lt;= std_logic_vector(to_signed(table_value,sine_vector_type'length));
    else
      wave_out &lt;= std_logic_vector(to_signed(-table_value,sine_vector_type'length));
    end if;
  end process;

end;
</PRE>
<H1>Lookup Table</H1>
<P>We will use a short Perl script to generate a lookup table in a package, 
<SPAN class=snippet>sine_package</SPAN>. Specify a word size and address size 
suitable for your application. Values of 8 and 7 will generate a ROM of size 256 
bytes. </P>
<P>
<FORM 
onsubmit="window.open('','testbench','width=800,height=600,scrollbars=yes,resizable=yes');return true" 
action=/cgi-bin/knowhow/vhdl_sine_gen.pl method=post target=testbench><INPUT 
size=4 value=7 name=word_size> Lookup table word size<BR><INPUT size=4 value=7 
name=address_size> Lookup table address size<BR><BR><INPUT type=submit value="Generate sine_package Code"> </FORM></P>
<H1>Test Bench</H1>
<P>Download an example sine wave generator with a test bench: <A 
href="http://www.doulos.com/knowhow/vhdl_designers_guide/models/sine_wave_generator/sine_testbench.zip">sine_testbench.zip</A> 
</P>
<P>We have bundled a simple testbench to show how this code works. There's also 
a Tcl script called <SPAN class=snippet>go.tcl</SPAN> to drive ModelSim for you. 
Here's what the output looks like in ModelSim. </P>
<P><IMG alt="Doulos: Training and Consultancy for FPGA/SoC Designers" 
src="Synthesisable Sine Wave Generator.files/wave.gif"> </P>
<H1>Synthesis</H1>
<P>Both Synplicity's Synplify

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