clock_splitter.tan.rpt

clock_spliter 採用彈性設計 , 可調整週期寬度.

; N/A           ; None        ; -2.900 ns ; enable ; clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[3]  ; clkin    ;
; N/A           ; None        ; -2.900 ns ; enable ; clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[5]  ; clkin    ;
; N/A           ; None        ; -2.900 ns ; enable ; clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[4]  ; clkin    ;
; N/A           ; None        ; -2.900 ns ; enable ; clk_divider:inst|clk_out                        ; clkin    ;
+---------------+-------------+-----------+--------+-------------------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Mon Feb 18 23:57:08 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off clock_splitter -c clock_splitter
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clkin" is an undefined clock
Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "clk_divider:inst3|clk_out" as buffer
    Info: Detected ripple clock "clk_divider:inst2|clk_out" as buffer
    Info: Detected ripple clock "clk_divider:inst1|clk_out" as buffer
    Info: Detected ripple clock "clk_divider:inst|clk_out" as buffer
Info: Clock "clkin" has Internal fmax of 94.34 MHz between source register "clk_divider:inst|clk_out" and destination register "clk_divider:inst|clk_out" (period= 10.6 ns)
    Info: + Longest register to register delay is 6.100 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 8; REG Node = 'clk_divider:inst|clk_out'
        Info: 2: + IC(3.300 ns) + CELL(2.800 ns) = 6.100 ns; Loc. = LC5; Fanout = 8; REG Node = 'clk_divider:inst|clk_out'
        Info: Total cell delay = 2.800 ns ( 45.90 % )
        Info: Total interconnect delay = 3.300 ns ( 54.10 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clkin" to destination register is 3.200 ns
            Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_125; Fanout = 7; CLK Node = 'clkin'
            Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC5; Fanout = 8; REG Node = 'clk_divider:inst|clk_out'
            Info: Total cell delay = 3.200 ns ( 100.00 % )
        Info: - Longest clock path from clock "clkin" to source register is 3.200 ns
            Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_125; Fanout = 7; CLK Node = 'clkin'
            Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC5; Fanout = 8; REG Node = 'clk_divider:inst|clk_out'
            Info: Total cell delay = 3.200 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.600 ns
    Info: + Micro setup delay of destination is 2.900 ns
Info: tsu for register "clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[0]" (data pin = "enable", clock pin = "clkin") is 7.000 ns
    Info: + Longest pin to register delay is 7.300 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_131; Fanout = 54; PIN Node = 'enable'
        Info: 2: + IC(3.300 ns) + CELL(2.800 ns) = 7.300 ns; Loc. = LC13; Fanout = 11; REG Node = 'clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[0]'
        Info: Total cell delay = 4.000 ns ( 54.79 % )
        Info: Total interconnect delay = 3.300 ns ( 45.21 % )
    Info: + Micro setup delay of destination is 2.900 ns
    Info: - Shortest clock path from clock "clkin" to destination register is 3.200 ns
        Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_125; Fanout = 7; CLK Node = 'clkin'
        Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC13; Fanout = 11; REG Node = 'clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[0]'
        Info: Total cell delay = 3.200 ns ( 100.00 % )
Info: tco from clock "clkin" to destination pin "6HZ" through register "clk_divider:inst4|clk_out" is 34.200 ns
    Info: + Longest clock path from clock "clkin" to source register is 31.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_125; Fanout = 7; CLK Node = 'clkin'
        Info: 2: + IC(0.000 ns) + CELL(2.400 ns) = 4.800 ns; Loc. = LC5; Fanout = 8; REG Node = 'clk_divider:inst|clk_out'
        Info: 3: + IC(3.300 ns) + CELL(3.700 ns) = 11.800 ns; Loc. = LC78; Fanout = 6; REG Node = 'clk_divider:inst1|clk_out'
        Info: 4: + IC(3.200 ns) + CELL(3.700 ns) = 18.700 ns; Loc. = LC77; Fanout = 7; REG Node = 'clk_divider:inst2|clk_out'
        Info: 5: + IC(3.300 ns) + CELL(3.700 ns) = 25.700 ns; Loc. = LC73; Fanout = 7; REG Node = 'clk_divider:inst3|clk_out'
        Info: 6: + IC(3.200 ns) + CELL(2.100 ns) = 31.000 ns; Loc. = LC69; Fanout = 2; REG Node = 'clk_divider:inst4|clk_out'
        Info: Total cell delay = 18.000 ns ( 58.06 % )
        Info: Total interconnect delay = 13.000 ns ( 41.94 % )
    Info: + Micro clock to output delay of source is 1.600 ns
    Info: + Longest register to pin delay is 1.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC69; Fanout = 2; REG Node = 'clk_divider:inst4|clk_out'
        Info: 2: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_138; Fanout = 0; PIN Node = '6HZ'
        Info: Total cell delay = 1.600 ns ( 100.00 % )
Info: th for register "clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[0]" (data pin = "enable", clock pin = "clkin") is 24.900 ns
    Info: + Longest clock path from clock "clkin" to destination register is 31.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_125; Fanout = 7; CLK Node = 'clkin'
        Info: 2: + IC(0.000 ns) + CELL(2.400 ns) = 4.800 ns; Loc. = LC5; Fanout = 8; REG Node = 'clk_divider:inst|clk_out'
        Info: 3: + IC(3.300 ns) + CELL(3.700 ns) = 11.800 ns; Loc. = LC78; Fanout = 6; REG Node = 'clk_divider:inst1|clk_out'
        Info: 4: + IC(3.200 ns) + CELL(3.700 ns) = 18.700 ns; Loc. = LC77; Fanout = 7; REG Node = 'clk_divider:inst2|clk_out'
        Info: 5: + IC(3.300 ns) + CELL(3.700 ns) = 25.700 ns; Loc. = LC73; Fanout = 7; REG Node = 'clk_divider:inst3|clk_out'
        Info: 6: + IC(3.200 ns) + CELL(2.100 ns) = 31.000 ns; Loc. = LC67; Fanout = 7; REG Node = 'clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[0]'
        Info: Total cell delay = 18.000 ns ( 58.06 % )
        Info: Total interconnect delay = 13.000 ns ( 41.94 % )
    Info: + Micro hold delay of destination is 1.200 ns
    Info: - Shortest pin to register delay is 7.300 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_131; Fanout = 54; PIN Node = 'enable'
        Info: 2: + IC(3.300 ns) + CELL(2.800 ns) = 7.300 ns; Loc. = LC67; Fanout = 7; REG Node = 'clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[0]'
        Info: Total cell delay = 4.000 ns ( 54.79 % )
        Info: Total interconnect delay = 3.300 ns ( 45.21 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Allocated 107 megabytes of memory during processing
    Info: Processing ended: Mon Feb 18 23:57:14 2008
    Info: Elapsed time: 00:00:06