clk_divider.fit.rpt

clock_spliter 採用彈性設計 , 可調整週期寬度.

+------+-------+-------+-------+--------------+------------+---------+


+-----------------------------------------------+
; Output Pin Default Load For Reported TCO      ;
+--------------+-------+------------------------+
; I/O Standard ; Load  ; Termination Resistance ;
+--------------+-------+------------------------+
; 3.3-V LVTTL  ; 10 pF ; Not Available          ;
; 3.3-V LVCMOS ; 10 pF ; Not Available          ;
; 3.3-V PCI    ; 10 pF ; 25 Ohm (Parallel)      ;
; 2.5 V        ; 10 pF ; Not Available          ;
+--------------+-------+------------------------+
Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.


+----------------------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity                                                              ;
+----------------------------+------------+------+------------------------------------+--------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name                ; Library Name ;
+----------------------------+------------+------+------------------------------------+--------------+
; |clk_divider               ; 5          ; 7    ; |clk_divider                       ; work         ;
;    |lpm_counter:cnt_rtl_0| ; 4          ; 0    ; |clk_divider|lpm_counter:cnt_rtl_0 ; work         ;
+----------------------------+------------+------+------------------------------------+--------------+


+----------------------------------------------------------------------------------------------------------------------+
; Control Signals                                                                                                      ;
+-------------------------------+----------+---------+--------------+--------+----------------------+------------------+
; Name                          ; Location ; Fan-Out ; Usage        ; Global ; Global Resource Used ; Global Line Name ;
+-------------------------------+----------+---------+--------------+--------+----------------------+------------------+
; clk                           ; PIN_125  ; 5       ; Clock        ; yes    ; On                   ; --               ;
; lpm_counter:cnt_rtl_0|dffs[0] ; LC1      ; 5       ; Async. clear ; no     ; --                   ; --               ;
; lpm_counter:cnt_rtl_0|dffs[1] ; LC2      ; 4       ; Async. clear ; no     ; --                   ; --               ;
; lpm_counter:cnt_rtl_0|dffs[2] ; LC5      ; 4       ; Async. clear ; no     ; --                   ; --               ;
; lpm_counter:cnt_rtl_0|dffs[3] ; LC4      ; 3       ; Async. clear ; no     ; --                   ; --               ;
+-------------------------------+----------+---------+--------------+--------+----------------------+------------------+


+---------------------------------------------------------------------+
; Global & Other Fast Signals                                         ;
+------+----------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+------+----------+---------+----------------------+------------------+
; clk  ; PIN_125  ; 5       ; On                   ; --               ;
+------+----------+---------+----------------------+------------------+


+-----------------------------------------+
; Non-Global High Fan-Out Signals         ;
+-------------------------------+---------+
; Name                          ; Fan-Out ;
+-------------------------------+---------+
; enable                        ; 5       ;
; lpm_counter:cnt_rtl_0|dffs[0] ; 5       ;
; lpm_counter:cnt_rtl_0|dffs[2] ; 4       ;
; lpm_counter:cnt_rtl_0|dffs[1] ; 4       ;
; lpm_counter:cnt_rtl_0|dffs[3] ; 3       ;
; clk_out~reg0                  ; 2       ;
+-------------------------------+---------+


+----------------------------------------------+
; Interconnect Usage Summary                   ;
+----------------------------+-----------------+
; Interconnect Resource Type ; Usage           ;
+----------------------------+-----------------+
; Output enables             ; 0 / 6 ( 0 % )   ;
; PIA buffers                ; 6 / 576 ( 1 % ) ;
; PIAs                       ; 6 / 576 ( 1 % ) ;
+----------------------------+-----------------+


+----------------------------------------------------------------------------+
; LAB External Interconnect                                                  ;
+----------------------------------------------+-----------------------------+
; LAB External Interconnects  (Average = 0.38) ; Number of LABs  (Total = 1) ;
+----------------------------------------------+-----------------------------+
; 0                                            ; 15                          ;
; 1                                            ; 0                           ;
; 2                                            ; 0                           ;
; 3                                            ; 0                           ;
; 4                                            ; 0                           ;
; 5                                            ; 0                           ;
; 6                                            ; 1                           ;
+----------------------------------------------+-----------------------------+


+----------------------------------------------------------------------+
; LAB Macrocells                                                       ;
+----------------------------------------+-----------------------------+
; Number of Macrocells  (Average = 0.31) ; Number of LABs  (Total = 1) ;
+----------------------------------------+-----------------------------+
; 0                                      ; 15                          ;
; 1                                      ; 0                           ;
; 2                                      ; 0                           ;
; 3                                      ; 0                           ;
; 4                                      ; 0                           ;
; 5                                      ; 1                           ;
+----------------------------------------+-----------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection                                                                                                                                                                                                                                                                                          ;
+-----+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input                                                                                                                                                 ; Output                                                                                                                                   ;
+-----+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------+
;  A  ; LC1        ; clk, lpm_counter:cnt_rtl_0|dffs[0], enable                                                                                                            ; lpm_counter:cnt_rtl_0|dffs[0], lpm_counter:cnt_rtl_0|dffs[1], lpm_counter:cnt_rtl_0|dffs[3], lpm_counter:cnt_rtl_0|dffs[2], clk_out~reg0 ;
;  A  ; LC2        ; clk, lpm_counter:cnt_rtl_0|dffs[2], enable, lpm_counter:cnt_rtl_0|dffs[1], lpm_counter:cnt_rtl_0|dffs[0], lpm_counter:cnt_rtl_0|dffs[3]               ; lpm_counter:cnt_rtl_0|dffs[1], lpm_counter:cnt_rtl_0|dffs[3], lpm_counter:cnt_rtl_0|dffs[2], clk_out~reg0                                ;
;  A  ; LC4        ; clk, enable, lpm_counter:cnt_rtl_0|dffs[1], lpm_counter:cnt_rtl_0|dffs[2], lpm_counter:cnt_rtl_0|dffs[0], lpm_counter:cnt_rtl_0|dffs[3]               ; lpm_counter:cnt_rtl_0|dffs[1], lpm_counter:cnt_rtl_0|dffs[3], clk_out~reg0                                                               ;
;  A  ; LC5        ; clk, enable, lpm_counter:cnt_rtl_0|dffs[1], lpm_counter:cnt_rtl_0|dffs[0], lpm_counter:cnt_rtl_0|dffs[2]                                              ; lpm_counter:cnt_rtl_0|dffs[1], lpm_counter:cnt_rtl_0|dffs[3], lpm_counter:cnt_rtl_0|dffs[2], clk_out~reg0                                ;
;  A  ; LC3        ; clk, clk_out~reg0, enable, lpm_counter:cnt_rtl_0|dffs[2], lpm_counter:cnt_rtl_0|dffs[0], lpm_counter:cnt_rtl_0|dffs[3], lpm_counter:cnt_rtl_0|dffs[1] ; clk_out~reg0, clk_out                                                                                                                    ;
+-----+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------+
; Fitter Device Options                                                                  ;
+----------------------------------------------+-----------------------------------------+
; Option                                       ; Setting                                 ;
+----------------------------------------------+-----------------------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                                     ;
; Enable device-wide reset (DEV_CLRn)          ; Off                                     ;
; Enable device-wide output enable (DEV_OE)    ; Off                                     ;
; Enable INIT_DONE output                      ; Off                                     ;
; Configuration scheme                         ; Passive Serial                          ;
; Reserve all unused pins                      ; As output driving an unspecified signal ;
; Security bit                                 ; Off                                     ;
; Base pin-out file on sameframe device        ; Off                                     ;
+----------------------------------------------+-----------------------------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition
    Info: Processing started: Fri Feb 15 15:04:28 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off clk_divider -c clk_divider
Info: Selected device EPM3256ATC144-10 for design "clk_divider"
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Allocated 140 megabytes of memory during processing
    Info: Processing ended: Fri Feb 15 15:04:36 2008
    Info: Elapsed time: 00:00:08