clock_splitter.tan.qmsg

clock_spliter 採用彈性設計 , 可調整週期寬度.

{ "Info" "ITDB_FULL_TCO_RESULT" "clkin 6HZ clk_divider:inst4\|clk_out 34.200 ns register " "Info: tco from clock \"clkin\" to destination pin \"6HZ\" through register \"clk_divider:inst4\|clk_out\" is 34.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 31.000 ns + Longest register " "Info: + Longest clock path from clock \"clkin\" to source register is 31.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 2.400 ns clkin 1 CLK PIN_125 7 " "Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_125; Fanout = 7; CLK Node = 'clkin'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "clock_splitter.bdf" "" { Schematic "I:/POWERCC_II_IP/clock_splitter/clock_splitter.bdf" { { 264 -192 -24 280 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 4.800 ns clk_divider:inst\|clk_out 2 REG LC5 8 " "Info: 2: + IC(0.000 ns) + CELL(2.400 ns) = 4.800 ns; Loc. = LC5; Fanout = 8; REG Node = 'clk_divider:inst\|clk_out'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { clkin clk_divider:inst|clk_out } "NODE_NAME" } } { "clk_divider.vhd" "" { Text "I:/POWERCC_II_IP/clock_splitter/clk_divider.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(3.700 ns) 11.800 ns clk_divider:inst1\|clk_out 3 REG LC78 6 " "Info: 3: + IC(3.300 ns) + CELL(3.700 ns) = 11.800 ns; Loc. = LC78; Fanout = 6; REG Node = 'clk_divider:inst1\|clk_out'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { clk_divider:inst|clk_out clk_divider:inst1|clk_out } "NODE_NAME" } } { "clk_divider.vhd" "" { Text "I:/POWERCC_II_IP/clock_splitter/clk_divider.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(3.700 ns) 18.700 ns clk_divider:inst2\|clk_out 4 REG LC77 7 " "Info: 4: + IC(3.200 ns) + CELL(3.700 ns) = 18.700 ns; Loc. = LC77; Fanout = 7; REG Node = 'clk_divider:inst2\|clk_out'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.900 ns" { clk_divider:inst1|clk_out clk_divider:inst2|clk_out } "NODE_NAME" } } { "clk_divider.vhd" "" { Text "I:/POWERCC_II_IP/clock_splitter/clk_divider.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(3.700 ns) 25.700 ns clk_divider:inst3\|clk_out 5 REG LC73 7 " "Info: 5: + IC(3.300 ns) + CELL(3.700 ns) = 25.700 ns; Loc. = LC73; Fanout = 7; REG Node = 'clk_divider:inst3\|clk_out'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { clk_divider:inst2|clk_out clk_divider:inst3|clk_out } "NODE_NAME" } } { "clk_divider.vhd" "" { Text "I:/POWERCC_II_IP/clock_splitter/clk_divider.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(2.100 ns) 31.000 ns clk_divider:inst4\|clk_out 6 REG LC69 2 " "Info: 6: + IC(3.200 ns) + CELL(2.100 ns) = 31.000 ns; Loc. = LC69; Fanout = 2; REG Node = 'clk_divider:inst4\|clk_out'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { clk_divider:inst3|clk_out clk_divider:inst4|clk_out } "NODE_NAME" } } { "clk_divider.vhd" "" { Text "I:/POWERCC_II_IP/clock_splitter/clk_divider.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "18.000 ns ( 58.06 % ) " "Info: Total cell delay = 18.000 ns ( 58.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.000 ns ( 41.94 % ) " "Info: Total interconnect delay = 13.000 ns ( 41.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "31.000 ns" { clkin clk_divider:inst|clk_out clk_divider:inst1|clk_out clk_divider:inst2|clk_out clk_divider:inst3|clk_out clk_divider:inst4|clk_out } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "31.000 ns" { clkin clkin~out clk_divider:inst|clk_out clk_divider:inst1|clk_out clk_divider:inst2|clk_out clk_divider:inst3|clk_out clk_divider:inst4|clk_out } { 0.000ns 0.000ns 0.000ns 3.300ns 3.200ns 3.300ns 3.200ns } { 0.000ns 2.400ns 2.400ns 3.700ns 3.700ns 3.700ns 2.100ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "clk_divider.vhd" "" { Text "I:/POWERCC_II_IP/clock_splitter/clk_divider.vhd" 36 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.600 ns + Longest register pin " "Info: + Longest register to pin delay is 1.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_divider:inst4\|clk_out 1 REG LC69 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC69; Fanout = 2; REG Node = 'clk_divider:inst4\|clk_out'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_divider:inst4|clk_out } "NODE_NAME" } } { "clk_divider.vhd" "" { Text "I:/POWERCC_II_IP/clock_splitter/clk_divider.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns 6HZ 2 PIN PIN_138 0 " "Info: 2: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_138; Fanout = 0; PIN Node = '6HZ'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { clk_divider:inst4|clk_out 6HZ } "NODE_NAME" } } { "clock_splitter.bdf" "" { Schematic "I:/POWERCC_II_IP/clock_splitter/clock_splitter.bdf" { { 776 584 760 792 "6HZ" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 100.00 % ) " "Info: Total cell delay = 1.600 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { clk_divider:inst4|clk_out 6HZ } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.600 ns" { clk_divider:inst4|clk_out 6HZ } { 0.000ns 0.000ns } { 0.000ns 1.600ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "31.000 ns" { clkin clk_divider:inst|clk_out clk_divider:inst1|clk_out clk_divider:inst2|clk_out clk_divider:inst3|clk_out clk_divider:inst4|clk_out } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "31.000 ns" { clkin clkin~out clk_divider:inst|clk_out clk_divider:inst1|clk_out clk_divider:inst2|clk_out clk_divider:inst3|clk_out clk_divider:inst4|clk_out } { 0.000ns 0.000ns 0.000ns 3.300ns 3.200ns 3.300ns 3.200ns } { 0.000ns 2.400ns 2.400ns 3.700ns 3.700ns 3.700ns 2.100ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { clk_divider:inst4|clk_out 6HZ } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.600 ns" { clk_divider:inst4|clk_out 6HZ } { 0.000ns 0.000ns } { 0.000ns 1.600ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "clk_divider:inst4\|lpm_counter:cnt_rtl_2\|dffs\[0\] enable clkin 24.900 ns register " "Info: th for register \"clk_divider:inst4\|lpm_counter:cnt_rtl_2\|dffs\[0\]\" (data pin = \"enable\", clock pin = \"clkin\") is 24.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 31.000 ns + Longest register " "Info: + Longest clock path from clock \"clkin\" to destination register is 31.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 2.400 ns clkin 1 CLK PIN_125 7 " "Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_125; Fanout = 7; CLK Node = 'clkin'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "clock_splitter.bdf" "" { Schematic "I:/POWERCC_II_IP/clock_splitter/clock_splitter.bdf" { { 264 -192 -24 280 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 4.800 ns clk_divider:inst\|clk_out 2 REG LC5 8 " "Info: 2: + IC(0.000 ns) + CELL(2.400 ns) = 4.800 ns; Loc. = LC5; Fanout = 8; REG Node = 'clk_divider:inst\|clk_out'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { clkin clk_divider:inst|clk_out } "NODE_NAME" } } { "clk_divider.vhd" "" { Text "I:/POWERCC_II_IP/clock_splitter/clk_divider.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(3.700 ns) 11.800 ns clk_divider:inst1\|clk_out 3 REG LC78 6 " "Info: 3: + IC(3.300 ns) + CELL(3.700 ns) = 11.800 ns; Loc. = LC78; Fanout = 6; REG Node = 'clk_divider:inst1\|clk_out'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { clk_divider:inst|clk_out clk_divider:inst1|clk_out } "NODE_NAME" } } { "clk_divider.vhd" "" { Text "I:/POWERCC_II_IP/clock_splitter/clk_divider.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(3.700 ns) 18.700 ns clk_divider:inst2\|clk_out 4 REG LC77 7 " "Info: 4: + IC(3.200 ns) + CELL(3.700 ns) = 18.700 ns; Loc. = LC77; Fanout = 7; REG Node = 'clk_divider:inst2\|clk_out'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.900 ns" { clk_divider:inst1|clk_out clk_divider:inst2|clk_out } "NODE_NAME" } } { "clk_divider.vhd" "" { Text "I:/POWERCC_II_IP/clock_splitter/clk_divider.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(3.700 ns) 25.700 ns clk_divider:inst3\|clk_out 5 REG LC73 7 " "Info: 5: + IC(3.300 ns) + CELL(3.700 ns) = 25.700 ns; Loc. = LC73; Fanout = 7; REG Node = 'clk_divider:inst3\|clk_out'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { clk_divider:inst2|clk_out clk_divider:inst3|clk_out } "NODE_NAME" } } { "clk_divider.vhd" "" { Text "I:/POWERCC_II_IP/clock_splitter/clk_divider.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(2.100 ns) 31.000 ns clk_divider:inst4\|lpm_counter:cnt_rtl_2\|dffs\[0\] 6 REG LC67 7 " "Info: 6: + IC(3.200 ns) + CELL(2.100 ns) = 31.000 ns; Loc. = LC67; Fanout = 7; REG Node = 'clk_divider:inst4\|lpm_counter:cnt_rtl_2\|dffs\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { clk_divider:inst3|clk_out clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "18.000 ns ( 58.06 % ) " "Info: Total cell delay = 18.000 ns ( 58.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.000 ns ( 41.94 % ) " "Info: Total interconnect delay = 13.000 ns ( 41.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "31.000 ns" { clkin clk_divider:inst|clk_out clk_divider:inst1|clk_out clk_divider:inst2|clk_out clk_divider:inst3|clk_out clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "31.000 ns" { clkin clkin~out clk_divider:inst|clk_out clk_divider:inst1|clk_out clk_divider:inst2|clk_out clk_divider:inst3|clk_out clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[0] } { 0.000ns 0.000ns 0.000ns 3.300ns 3.200ns 3.300ns 3.200ns } { 0.000ns 2.400ns 2.400ns 3.700ns 3.700ns 3.700ns 2.100ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "1.200 ns + " "Info: + Micro hold delay of destination is 1.200 ns" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.300 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns enable 1 PIN PIN_131 54 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_131; Fanout = 54; PIN Node = 'enable'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { enable } "NODE_NAME" } } { "clock_splitter.bdf" "" { Schematic "I:/POWERCC_II_IP/clock_splitter/clock_splitter.bdf" { { 360 -192 -24 376 "enable" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(2.800 ns) 7.300 ns clk_divider:inst4\|lpm_counter:cnt_rtl_2\|dffs\[0\] 2 REG LC67 7 " "Info: 2: + IC(3.300 ns) + CELL(2.800 ns) = 7.300 ns; Loc. = LC67; Fanout = 7; REG Node = 'clk_divider:inst4\|lpm_counter:cnt_rtl_2\|dffs\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.100 ns" { enable clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns ( 54.79 % ) " "Info: Total cell delay = 4.000 ns ( 54.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.300 ns ( 45.21 % ) " "Info: Total interconnect delay = 3.300 ns ( 45.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.300 ns" { enable clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.300 ns" { enable enable~out clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[0] } { 0.000ns 0.000ns 3.300ns } { 0.000ns 1.200ns 2.800ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "31.000 ns" { clkin clk_divider:inst|clk_out clk_divider:inst1|clk_out clk_divider:inst2|clk_out clk_divider:inst3|clk_out clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "31.000 ns" { clkin clkin~out clk_divider:inst|clk_out clk_divider:inst1|clk_out clk_divider:inst2|clk_out clk_divider:inst3|clk_out clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[0] } { 0.000ns 0.000ns 0.000ns 3.300ns 3.200ns 3.300ns 3.200ns } { 0.000ns 2.400ns 2.400ns 3.700ns 3.700ns 3.700ns 2.100ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.300 ns" { enable clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.300 ns" { enable enable~out clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[0] } { 0.000ns 0.000ns 3.300ns } { 0.000ns 1.200ns 2.800ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "107 " "Info: Allocated 107 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Feb 18 23:57:14 2008 " "Info: Processing ended: Mon Feb 18 23:57:14 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}