clock_splitter.tan.qmsg

clock_spliter 採用彈性設計 , 可調整週期寬度.

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clkin " "Info: Assuming node \"clkin\" is an undefined clock" {  } { { "clock_splitter.bdf" "" { Schematic "I:/POWERCC_II_IP/clock_splitter/clock_splitter.bdf" { { 264 -192 -24 280 "clkin" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "clkin" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk_divider:inst3\|clk_out " "Info: Detected ripple clock \"clk_divider:inst3\|clk_out\" as buffer" {  } { { "clk_divider.vhd" "" { Text "I:/POWERCC_II_IP/clock_splitter/clk_divider.vhd" 36 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_divider:inst3\|clk_out" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clk_divider:inst2\|clk_out " "Info: Detected ripple clock \"clk_divider:inst2\|clk_out\" as buffer" {  } { { "clk_divider.vhd" "" { Text "I:/POWERCC_II_IP/clock_splitter/clk_divider.vhd" 36 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_divider:inst2\|clk_out" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clk_divider:inst1\|clk_out " "Info: Detected ripple clock \"clk_divider:inst1\|clk_out\" as buffer" {  } { { "clk_divider.vhd" "" { Text "I:/POWERCC_II_IP/clock_splitter/clk_divider.vhd" 36 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_divider:inst1\|clk_out" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clk_divider:inst\|clk_out " "Info: Detected ripple clock \"clk_divider:inst\|clk_out\" as buffer" {  } { { "clk_divider.vhd" "" { Text "I:/POWERCC_II_IP/clock_splitter/clk_divider.vhd" 36 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_divider:inst\|clk_out" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clkin register clk_divider:inst\|clk_out register clk_divider:inst\|clk_out 94.34 MHz 10.6 ns Internal " "Info: Clock \"clkin\" has Internal fmax of 94.34 MHz between source register \"clk_divider:inst\|clk_out\" and destination register \"clk_divider:inst\|clk_out\" (period= 10.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.100 ns + Longest register register " "Info: + Longest register to register delay is 6.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_divider:inst\|clk_out 1 REG LC5 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 8; REG Node = 'clk_divider:inst\|clk_out'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_divider:inst|clk_out } "NODE_NAME" } } { "clk_divider.vhd" "" { Text "I:/POWERCC_II_IP/clock_splitter/clk_divider.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(2.800 ns) 6.100 ns clk_divider:inst\|clk_out 2 REG LC5 8 " "Info: 2: + IC(3.300 ns) + CELL(2.800 ns) = 6.100 ns; Loc. = LC5; Fanout = 8; REG Node = 'clk_divider:inst\|clk_out'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.100 ns" { clk_divider:inst|clk_out clk_divider:inst|clk_out } "NODE_NAME" } } { "clk_divider.vhd" "" { Text "I:/POWERCC_II_IP/clock_splitter/clk_divider.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 45.90 % ) " "Info: Total cell delay = 2.800 ns ( 45.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.300 ns ( 54.10 % ) " "Info: Total interconnect delay = 3.300 ns ( 54.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.100 ns" { clk_divider:inst|clk_out clk_divider:inst|clk_out } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.100 ns" { clk_divider:inst|clk_out clk_divider:inst|clk_out } { 0.000ns 3.300ns } { 0.000ns 2.800ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 3.200 ns + Shortest register " "Info: + Shortest clock path from clock \"clkin\" to destination register is 3.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 2.400 ns clkin 1 CLK PIN_125 7 " "Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_125; Fanout = 7; CLK Node = 'clkin'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "clock_splitter.bdf" "" { Schematic "I:/POWERCC_II_IP/clock_splitter/clock_splitter.bdf" { { 264 -192 -24 280 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 3.200 ns clk_divider:inst\|clk_out 2 REG LC5 8 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC5; Fanout = 8; REG Node = 'clk_divider:inst\|clk_out'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { clkin clk_divider:inst|clk_out } "NODE_NAME" } } { "clk_divider.vhd" "" { Text "I:/POWERCC_II_IP/clock_splitter/clk_divider.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns ( 100.00 % ) " "Info: Total cell delay = 3.200 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { clkin clk_divider:inst|clk_out } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.200 ns" { clkin clkin~out clk_divider:inst|clk_out } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 3.200 ns - Longest register " "Info: - Longest clock path from clock \"clkin\" to source register is 3.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 2.400 ns clkin 1 CLK PIN_125 7 " "Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_125; Fanout = 7; CLK Node = 'clkin'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "clock_splitter.bdf" "" { Schematic "I:/POWERCC_II_IP/clock_splitter/clock_splitter.bdf" { { 264 -192 -24 280 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 3.200 ns clk_divider:inst\|clk_out 2 REG LC5 8 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC5; Fanout = 8; REG Node = 'clk_divider:inst\|clk_out'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { clkin clk_divider:inst|clk_out } "NODE_NAME" } } { "clk_divider.vhd" "" { Text "I:/POWERCC_II_IP/clock_splitter/clk_divider.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns ( 100.00 % ) " "Info: Total cell delay = 3.200 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { clkin clk_divider:inst|clk_out } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.200 ns" { clkin clkin~out clk_divider:inst|clk_out } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { clkin clk_divider:inst|clk_out } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.200 ns" { clkin clkin~out clk_divider:inst|clk_out } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { clkin clk_divider:inst|clk_out } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.200 ns" { clkin clkin~out clk_divider:inst|clk_out } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "clk_divider.vhd" "" { Text "I:/POWERCC_II_IP/clock_splitter/clk_divider.vhd" 36 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "clk_divider.vhd" "" { Text "I:/POWERCC_II_IP/clock_splitter/clk_divider.vhd" 36 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.100 ns" { clk_divider:inst|clk_out clk_divider:inst|clk_out } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.100 ns" { clk_divider:inst|clk_out clk_divider:inst|clk_out } { 0.000ns 3.300ns } { 0.000ns 2.800ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { clkin clk_divider:inst|clk_out } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.200 ns" { clkin clkin~out clk_divider:inst|clk_out } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { clkin clk_divider:inst|clk_out } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.200 ns" { clkin clkin~out clk_divider:inst|clk_out } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "clk_divider:inst\|lpm_counter:cnt_rtl_4\|dffs\[0\] enable clkin 7.000 ns register " "Info: tsu for register \"clk_divider:inst\|lpm_counter:cnt_rtl_4\|dffs\[0\]\" (data pin = \"enable\", clock pin = \"clkin\") is 7.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.300 ns + Longest pin register " "Info: + Longest pin to register delay is 7.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns enable 1 PIN PIN_131 54 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_131; Fanout = 54; PIN Node = 'enable'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { enable } "NODE_NAME" } } { "clock_splitter.bdf" "" { Schematic "I:/POWERCC_II_IP/clock_splitter/clock_splitter.bdf" { { 360 -192 -24 376 "enable" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(2.800 ns) 7.300 ns clk_divider:inst\|lpm_counter:cnt_rtl_4\|dffs\[0\] 2 REG LC13 11 " "Info: 2: + IC(3.300 ns) + CELL(2.800 ns) = 7.300 ns; Loc. = LC13; Fanout = 11; REG Node = 'clk_divider:inst\|lpm_counter:cnt_rtl_4\|dffs\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.100 ns" { enable clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns ( 54.79 % ) " "Info: Total cell delay = 4.000 ns ( 54.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.300 ns ( 45.21 % ) " "Info: Total interconnect delay = 3.300 ns ( 45.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.300 ns" { enable clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.300 ns" { enable enable~out clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[0] } { 0.000ns 0.000ns 3.300ns } { 0.000ns 1.200ns 2.800ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 3.200 ns - Shortest register " "Info: - Shortest clock path from clock \"clkin\" to destination register is 3.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 2.400 ns clkin 1 CLK PIN_125 7 " "Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_125; Fanout = 7; CLK Node = 'clkin'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "clock_splitter.bdf" "" { Schematic "I:/POWERCC_II_IP/clock_splitter/clock_splitter.bdf" { { 264 -192 -24 280 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 3.200 ns clk_divider:inst\|lpm_counter:cnt_rtl_4\|dffs\[0\] 2 REG LC13 11 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC13; Fanout = 11; REG Node = 'clk_divider:inst\|lpm_counter:cnt_rtl_4\|dffs\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { clkin clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns ( 100.00 % ) " "Info: Total cell delay = 3.200 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { clkin clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.200 ns" { clkin clkin~out clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.300 ns" { enable clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.300 ns" { enable enable~out clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[0] } { 0.000ns 0.000ns 3.300ns } { 0.000ns 1.200ns 2.800ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { clkin clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.200 ns" { clkin clkin~out clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}