clk_divider.vhd

clock_spliter 採用彈性設計 , 可調整週期寬度.

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--
-- File:	clk_divider.vhd
--
-- VHDL code to implement a clock divider.
-- The generic value 'modulus' is used to change the length of the count
-- Duty is how many clocks the output will stay low for, before going high
--
-- 14 Feb 2008 
-- Joseph Wen
---------------------------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;

PACKAGE clk_divider_package IS
	COMPONENT clk_divider
		GENERIC ( modulus	: INTEGER := 10;	-- Set Counter Modulus to 10
				  duty 		: INTEGER := 5);	-- Sets Duty cycle.    
   		
	PORT(	clk       	: IN  STD_LOGIC;
			enable		: IN  STD_LOGIC;
			clk_out		: OUT STD_LOGIC);
	END COMPONENT;
END clk_divider_package;

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY clk_divider IS
	GENERIC ( 	modulus		: INTEGER := 10;	-- Set Counter Modulus to 10
				duty 		: INTEGER := 5 );	-- Sets Duty cycle.    

	PORT(	clk       	: IN  STD_LOGIC;
			enable		: IN  STD_LOGIC;
			clk_out		: OUT STD_LOGIC);
END clk_divider;

ARCHITECTURE Behaviour OF clk_divider IS
BEGIN
	-- A clock divider
	PROCESS (clk)
      VARIABLE   cnt        : INTEGER RANGE 0 TO modulus := 0;
   	BEGIN
		IF (clk'EVENT AND clk = '1') THEN
      		IF (enable = '0') THEN
				cnt := 0;
				clk_out <= '0';
         	ELSE
				IF cnt = 0 THEN
					clk_out <= '1';
				END IF;
			
				IF cnt = modulus - 1 THEN
            		cnt := 0;
         		ELSE
            		cnt := cnt + 1;
         		END IF;
			END IF;
		END IF;
		
		IF cnt = duty THEN
			clk_out <= '0';
      	END IF;
   
   	END PROCESS;

END Behaviour;