clk_divider.tan.rpt

clock_spliter 採用彈性設計 , 可調整週期寬度.

+-------+----------------------------------+-------------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------------------------------+
; tsu                                                                                   ;
+-------+--------------+------------+--------+-------------------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From   ; To                            ; To Clock ;
+-------+--------------+------------+--------+-------------------------------+----------+
; N/A   ; None         ; 6.900 ns   ; enable ; lpm_counter:cnt_rtl_0|dffs[0] ; clk      ;
; N/A   ; None         ; 6.900 ns   ; enable ; lpm_counter:cnt_rtl_0|dffs[1] ; clk      ;
; N/A   ; None         ; 6.900 ns   ; enable ; lpm_counter:cnt_rtl_0|dffs[2] ; clk      ;
; N/A   ; None         ; 6.900 ns   ; enable ; lpm_counter:cnt_rtl_0|dffs[3] ; clk      ;
; N/A   ; None         ; 6.900 ns   ; enable ; clk_out~reg0                  ; clk      ;
+-------+--------------+------------+--------+-------------------------------+----------+


+-------------------------------------------------------------------------+
; tco                                                                     ;
+-------+--------------+------------+--------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To      ; From Clock ;
+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 6.400 ns   ; clk_out~reg0 ; clk_out ; clk        ;
+-------+--------------+------------+--------------+---------+------------+


+---------------------------------------------------------------------------------------------+
; th                                                                                          ;
+---------------+-------------+-----------+--------+-------------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To                            ; To Clock ;
+---------------+-------------+-----------+--------+-------------------------------+----------+
; N/A           ; None        ; -2.800 ns ; enable ; lpm_counter:cnt_rtl_0|dffs[0] ; clk      ;
; N/A           ; None        ; -2.800 ns ; enable ; lpm_counter:cnt_rtl_0|dffs[1] ; clk      ;
; N/A           ; None        ; -2.800 ns ; enable ; lpm_counter:cnt_rtl_0|dffs[2] ; clk      ;
; N/A           ; None        ; -2.800 ns ; enable ; lpm_counter:cnt_rtl_0|dffs[3] ; clk      ;
; N/A           ; None        ; -2.800 ns ; enable ; clk_out~reg0                  ; clk      ;
+---------------+-------------+-----------+--------+-------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition
    Info: Processing started: Fri Feb 15 15:05:00 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off clk_divider -c clk_divider
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 95.24 MHz between source register "lpm_counter:cnt_rtl_0|dffs[0]" and destination register "lpm_counter:cnt_rtl_0|dffs[0]" (period= 10.5 ns)
    Info: + Longest register to register delay is 6.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 9; REG Node = 'lpm_counter:cnt_rtl_0|dffs[0]'
        Info: 2: + IC(3.200 ns) + CELL(2.800 ns) = 6.000 ns; Loc. = LC1; Fanout = 9; REG Node = 'lpm_counter:cnt_rtl_0|dffs[0]'
        Info: Total cell delay = 2.800 ns ( 46.67 % )
        Info: Total interconnect delay = 3.200 ns ( 53.33 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.200 ns
            Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_125; Fanout = 5; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC1; Fanout = 9; REG Node = 'lpm_counter:cnt_rtl_0|dffs[0]'
            Info: Total cell delay = 3.200 ns ( 100.00 % )
        Info: - Longest clock path from clock "clk" to source register is 3.200 ns
            Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_125; Fanout = 5; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC1; Fanout = 9; REG Node = 'lpm_counter:cnt_rtl_0|dffs[0]'
            Info: Total cell delay = 3.200 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.600 ns
    Info: + Micro setup delay of destination is 2.900 ns
Info: tsu for register "lpm_counter:cnt_rtl_0|dffs[0]" (data pin = "enable", clock pin = "clk") is 6.900 ns
    Info: + Longest pin to register delay is 7.200 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_81; Fanout = 10; PIN Node = 'enable'
        Info: 2: + IC(3.200 ns) + CELL(2.800 ns) = 7.200 ns; Loc. = LC1; Fanout = 9; REG Node = 'lpm_counter:cnt_rtl_0|dffs[0]'
        Info: Total cell delay = 4.000 ns ( 55.56 % )
        Info: Total interconnect delay = 3.200 ns ( 44.44 % )
    Info: + Micro setup delay of destination is 2.900 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.200 ns
        Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_125; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC1; Fanout = 9; REG Node = 'lpm_counter:cnt_rtl_0|dffs[0]'
        Info: Total cell delay = 3.200 ns ( 100.00 % )
Info: tco from clock "clk" to destination pin "clk_out" through register "clk_out~reg0" is 6.400 ns
    Info: + Longest clock path from clock "clk" to source register is 3.200 ns
        Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_125; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC3; Fanout = 2; REG Node = 'clk_out~reg0'
        Info: Total cell delay = 3.200 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.600 ns
    Info: + Longest register to pin delay is 1.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 2; REG Node = 'clk_out~reg0'
        Info: 2: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_2; Fanout = 0; PIN Node = 'clk_out'
        Info: Total cell delay = 1.600 ns ( 100.00 % )
Info: th for register "lpm_counter:cnt_rtl_0|dffs[0]" (data pin = "enable", clock pin = "clk") is -2.800 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.200 ns
        Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_125; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC1; Fanout = 9; REG Node = 'lpm_counter:cnt_rtl_0|dffs[0]'
        Info: Total cell delay = 3.200 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 1.200 ns
    Info: - Shortest pin to register delay is 7.200 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_81; Fanout = 10; PIN Node = 'enable'
        Info: 2: + IC(3.200 ns) + CELL(2.800 ns) = 7.200 ns; Loc. = LC1; Fanout = 9; REG Node = 'lpm_counter:cnt_rtl_0|dffs[0]'
        Info: Total cell delay = 4.000 ns ( 55.56 % )
        Info: Total interconnect delay = 3.200 ns ( 44.44 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Allocated 107 megabytes of memory during processing
    Info: Processing ended: Fri Feb 15 15:05:09 2008
    Info: Elapsed time: 00:00:09