clk_divider.map.rpt

clock_spliter 採用彈性設計 , 可調整週期寬度.

; alt_synch_counter_f.inc          ; yes             ; Megafunction    ; d:/altera/71/quartus/libraries/megafunctions/alt_synch_counter_f.inc ;
; alt_counter_f10ke.inc            ; yes             ; Megafunction    ; d:/altera/71/quartus/libraries/megafunctions/alt_counter_f10ke.inc   ;
; alt_counter_stratix.inc          ; yes             ; Megafunction    ; d:/altera/71/quartus/libraries/megafunctions/alt_counter_stratix.inc ;
; aglobal71.inc                    ; yes             ; Megafunction    ; d:/altera/71/quartus/libraries/megafunctions/aglobal71.inc           ;
+----------------------------------+-----------------+-----------------+----------------------------------------------------------------------+


+------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary          ;
+----------------------+-------------------------------+
; Resource             ; Usage                         ;
+----------------------+-------------------------------+
; Logic cells          ; 5                             ;
; Total registers      ; 5                             ;
; I/O pins             ; 3                             ;
; Maximum fan-out node ; lpm_counter:cnt_rtl_0|dffs[0] ;
; Maximum fan-out      ; 5                             ;
; Total fan-out        ; 28                            ;
; Average fan-out      ; 3.50                          ;
+----------------------+-------------------------------+


+----------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                ;
+----------------------------+------------+------+------------------------------------+--------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name                ; Library Name ;
+----------------------------+------------+------+------------------------------------+--------------+
; |clk_divider               ; 5          ; 3    ; |clk_divider                       ; work         ;
;    |lpm_counter:cnt_rtl_0| ; 4          ; 0    ; |clk_divider|lpm_counter:cnt_rtl_0 ; work         ;
+----------------------------+------------+------+------------------------------------+--------------+


+-----------------------------------------------+
; Source assignments for lpm_counter:cnt_rtl_0  ;
+---------------------------+-------+------+----+
; Assignment                ; Value ; From ; To ;
+---------------------------+-------+------+----+
; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -  ;
; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -  ;
; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -  ;
+---------------------------+-------+------+----+


+-----------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |clk_divider ;
+----------------+-------+----------------------------------------------------+
; Parameter Name ; Value ; Type                                               ;
+----------------+-------+----------------------------------------------------+
; modulus        ; 10    ; Signed Integer                                     ;
; duty           ; 5     ; Signed Integer                                     ;
+----------------+-------+----------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_counter:cnt_rtl_0 ;
+------------------------+-------------------+---------------------------+
; Parameter Name         ; Value             ; Type                      ;
+------------------------+-------------------+---------------------------+
; AUTO_CARRY_CHAINS      ; ON                ; AUTO_CARRY                ;
; IGNORE_CARRY_BUFFERS   ; OFF               ; IGNORE_CARRY              ;
; AUTO_CASCADE_CHAINS    ; ON                ; AUTO_CASCADE              ;
; IGNORE_CASCADE_BUFFERS ; OFF               ; IGNORE_CASCADE            ;
; LPM_WIDTH              ; 4                 ; Untyped                   ;
; LPM_DIRECTION          ; UP                ; Untyped                   ;
; LPM_MODULUS            ; 0                 ; Untyped                   ;
; LPM_AVALUE             ; UNUSED            ; Untyped                   ;
; LPM_SVALUE             ; UNUSED            ; Untyped                   ;
; LPM_PORT_UPDOWN        ; PORT_CONNECTIVITY ; Untyped                   ;
; DEVICE_FAMILY          ; MAX3000A          ; Untyped                   ;
; CARRY_CHAIN            ; MANUAL            ; Untyped                   ;
; CARRY_CHAIN_LENGTH     ; 48                ; CARRY_CHAIN_LENGTH        ;
; NOT_GATE_PUSH_BACK     ; ON                ; NOT_GATE_PUSH_BACK        ;
; CARRY_CNT_EN           ; SMART             ; Untyped                   ;
; LABWIDE_SCLR           ; ON                ; Untyped                   ;
; USE_NEW_VERSION        ; TRUE              ; Untyped                   ;
; CBXI_PARAMETER         ; NOTHING           ; Untyped                   ;
+------------------------+-------------------+---------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition
    Info: Processing started: Fri Feb 15 15:04:13 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clk_divider -c clk_divider
Info: Found 3 design units, including 1 entities, in source file clk_divider.vhd
    Info: Found design unit 1: clk_divider_package
    Info: Found design unit 2: clk_divider-Behaviour
    Info: Found entity 1: clk_divider
Info: Found 1 design units, including 1 entities, in source file clock_splitter.bdf
    Info: Found entity 1: clock_splitter
Info: Elaborating entity "clk_divider" for the top level hierarchy
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "cnt[0]~12"
Info: Found 1 design units, including 1 entities, in source file ../altera/71/quartus/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Elaborated megafunction instantiation "lpm_counter:cnt_rtl_0"
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "clk" to global clock signal
Info: Implemented 8 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 1 output pins
    Info: Implemented 5 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Allocated 150 megabytes of memory during processing
    Info: Processing ended: Fri Feb 15 15:04:23 2008
    Info: Elapsed time: 00:00:10