clk_divider.map.rpt

clock_spliter 採用彈性設計 , 可調整週期寬度.

Analysis & Synthesis report for clk_divider
Fri Feb 15 15:04:22 2008
Quartus II Version 7.1 Build 156 04/30/2007 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Source assignments for lpm_counter:cnt_rtl_0
  8. Parameter Settings for User Entity Instance: Top-level Entity: |clk_divider
  9. Parameter Settings for Inferred Entity Instance: lpm_counter:cnt_rtl_0
 10. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------+
; Analysis & Synthesis Summary                                          ;
+-----------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Successful - Fri Feb 15 15:04:22 2008   ;
; Quartus II Version          ; 7.1 Build 156 04/30/2007 SJ Web Edition ;
; Revision Name               ; clk_divider                             ;
; Top-level Entity Name       ; clk_divider                             ;
; Family                      ; MAX3000A                                ;
; Total macrocells            ; 5                                       ;
; Total pins                  ; 3                                       ;
+-----------------------------+-----------------------------------------+


+---------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                           ;
+----------------------------------------------------------------------+------------------+---------------+
; Option                                                               ; Setting          ; Default Value ;
+----------------------------------------------------------------------+------------------+---------------+
; Device                                                               ; EPM3256ATC144-10 ;               ;
; Top-level entity name                                                ; clk_divider      ; clk_divider   ;
; Family name                                                          ; MAX3000A         ; Stratix II    ;
; Create Debugging Nodes for IP Cores                                  ; Off              ; Off           ;
; Preserve fewer node names                                            ; On               ; On            ;
; Disable OpenCore Plus hardware evaluation                            ; Off              ; Off           ;
; Verilog Version                                                      ; Verilog_2001     ; Verilog_2001  ;
; VHDL Version                                                         ; VHDL93           ; VHDL93        ;
; State Machine Processing                                             ; Auto             ; Auto          ;
; Safe State Machine                                                   ; Off              ; Off           ;
; Extract Verilog State Machines                                       ; On               ; On            ;
; Extract VHDL State Machines                                          ; On               ; On            ;
; Ignore Verilog initial constructs                                    ; Off              ; Off           ;
; Add Pass-Through Logic to Inferred RAMs                              ; On               ; On            ;
; NOT Gate Push-Back                                                   ; On               ; On            ;
; Power-Up Don't Care                                                  ; On               ; On            ;
; Remove Duplicate Registers                                           ; On               ; On            ;
; Ignore CARRY Buffers                                                 ; Off              ; Off           ;
; Ignore CASCADE Buffers                                               ; Off              ; Off           ;
; Ignore GLOBAL Buffers                                                ; Off              ; Off           ;
; Ignore ROW GLOBAL Buffers                                            ; Off              ; Off           ;
; Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A           ; Auto             ; Auto          ;
; Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A            ; Off              ; Off           ;
; Limit AHDL Integers to 32 Bits                                       ; Off              ; Off           ;
; Optimization Technique -- MAX 7000B/7000AE/3000A/7000S/7000A         ; Speed            ; Speed         ;
; Allow XOR Gate Usage                                                 ; On               ; On            ;
; Auto Logic Cell Insertion                                            ; On               ; On            ;
; Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A ; 4                ; 4             ;
; Auto Parallel Expanders                                              ; On               ; On            ;
; Auto Open-Drain Pins                                                 ; On               ; On            ;
; Auto Resource Sharing                                                ; Off              ; Off           ;
; Maximum Fan-in Per Macrocell -- MAX 7000B/7000AE/3000A/7000S/7000A   ; 100              ; 100           ;
; Ignore translate_off and synthesis_off directives                    ; Off              ; Off           ;
; Show Parameter Settings Tables in Synthesis Report                   ; On               ; On            ;
; HDL message level                                                    ; Level2           ; Level2        ;
; Suppress Register Optimization Related Messages                      ; Off              ; Off           ;
; Number of Removed Registers Reported in Synthesis Report             ; 100              ; 100           ;
; Use smart compilation                                                ; Off              ; Off           ;
+----------------------------------------------------------------------+------------------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                      ;
+----------------------------------+-----------------+-----------------+----------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                                         ;
+----------------------------------+-----------------+-----------------+----------------------------------------------------------------------+
; clk_divider.vhd                  ; yes             ; User VHDL File  ; D:/splitter/clk_divider.vhd                                          ;
; lpm_counter.tdf                  ; yes             ; Megafunction    ; d:/altera/71/quartus/libraries/megafunctions/lpm_counter.tdf         ;
; lpm_constant.inc                 ; yes             ; Megafunction    ; d:/altera/71/quartus/libraries/megafunctions/lpm_constant.inc        ;
; lpm_decode.inc                   ; yes             ; Megafunction    ; d:/altera/71/quartus/libraries/megafunctions/lpm_decode.inc          ;
; lpm_add_sub.inc                  ; yes             ; Megafunction    ; d:/altera/71/quartus/libraries/megafunctions/lpm_add_sub.inc         ;
; cmpconst.inc                     ; yes             ; Megafunction    ; d:/altera/71/quartus/libraries/megafunctions/cmpconst.inc            ;
; lpm_compare.inc                  ; yes             ; Megafunction    ; d:/altera/71/quartus/libraries/megafunctions/lpm_compare.inc         ;
; lpm_counter.inc                  ; yes             ; Megafunction    ; d:/altera/71/quartus/libraries/megafunctions/lpm_counter.inc         ;
; dffeea.inc                       ; yes             ; Megafunction    ; d:/altera/71/quartus/libraries/megafunctions/dffeea.inc              ;
; alt_synch_counter.inc            ; yes             ; Megafunction    ; d:/altera/71/quartus/libraries/megafunctions/alt_synch_counter.inc   ;