📄 clock_splitter.fit.rpt
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; Output enables ; 0 / 6 ( 0 % ) ;
; PIA buffers ; 39 / 576 ( 7 % ) ;
; PIAs ; 39 / 576 ( 7 % ) ;
+----------------------------+------------------+
+----------------------------------------------------------------------------+
; LAB External Interconnect ;
+----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 2.44) ; Number of LABs (Total = 2) ;
+----------------------------------------------+-----------------------------+
; 0 - 1 ; 14 ;
; 2 - 3 ; 0 ;
; 4 - 5 ; 0 ;
; 6 - 7 ; 0 ;
; 8 - 9 ; 0 ;
; 10 - 11 ; 0 ;
; 12 - 13 ; 0 ;
; 14 - 15 ; 1 ;
; 16 - 17 ; 0 ;
; 18 - 19 ; 0 ;
; 20 - 21 ; 0 ;
; 22 - 23 ; 0 ;
; 24 - 25 ; 1 ;
+----------------------------------------------+-----------------------------+
+----------------------------------------------------------------------+
; LAB Macrocells ;
+----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 1.81) ; Number of LABs (Total = 2) ;
+----------------------------------------+-----------------------------+
; 0 ; 14 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 1 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 1 ;
+----------------------------------------+-----------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC13 ; clkin, enable, clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[0] ; clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[0], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[1], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[2], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[3], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[5], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[4], clk_divider:inst|clk_out ;
; A ; LC8 ; clkin, enable, clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[0], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[1] ; clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[1], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[2], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[3], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[5], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[4], clk_divider:inst|clk_out ;
; A ; LC9 ; clkin, enable, clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[1], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[0], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[2] ; clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[2], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[3], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[5], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[4], clk_divider:inst|clk_out ;
; A ; LC10 ; clkin, enable, clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[1], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[2], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[0], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[3] ; clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[3], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[5], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[4], clk_divider:inst|clk_out ;
; A ; LC11 ; clkin, clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[4], enable, clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[1], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[2], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[3], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[0], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[5] ; clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[5], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[4], clk_divider:inst|clk_out ;
; A ; LC12 ; clkin, clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[5], enable, clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[1], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[2], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[3], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[0], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[4] ; clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[5], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[4], clk_divider:inst|clk_out ;
; A ; LC5 ; clkin, enable, clk_divider:inst|clk_out, clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[4], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[3], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[5], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[2], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[1], clk_divider:inst|lpm_counter:cnt_rtl_4|dffs[0] ; clk_divider:inst|clk_out, clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[0], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[1], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[2], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[3], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[5], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[4], clk_divider:inst1|clk_out ;
; A ; LC6 ; enable, clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[0], clk_divider:inst|clk_out ; clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[0], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[1], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[2], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[3], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[5], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[4], clk_divider:inst1|clk_out ;
; A ; LC7 ; enable, clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[0], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[1], clk_divider:inst|clk_out ; clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[1], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[2], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[3], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[5], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[4], clk_divider:inst1|clk_out ;
; A ; LC1 ; enable, clk_divider:inst3|lpm_counter:cnt_rtl_1|dffs[0], clk_divider:inst2|clk_out ; clk_divider:inst3|lpm_counter:cnt_rtl_1|dffs[0], clk_divider:inst3|lpm_counter:cnt_rtl_1|dffs[1], clk_divider:inst3|lpm_counter:cnt_rtl_1|dffs[3], clk_divider:inst3|lpm_counter:cnt_rtl_1|dffs[2], clk_divider:inst3|clk_out ;
; A ; LC2 ; clk_divider:inst3|lpm_counter:cnt_rtl_1|dffs[2], enable, clk_divider:inst3|lpm_counter:cnt_rtl_1|dffs[1], clk_divider:inst3|lpm_counter:cnt_rtl_1|dffs[0], clk_divider:inst3|lpm_counter:cnt_rtl_1|dffs[3], clk_divider:inst2|clk_out ; clk_divider:inst3|lpm_counter:cnt_rtl_1|dffs[1], clk_divider:inst3|lpm_counter:cnt_rtl_1|dffs[3], clk_divider:inst3|lpm_counter:cnt_rtl_1|dffs[2], clk_divider:inst3|clk_out ;
; A ; LC3 ; enable, clk_divider:inst3|lpm_counter:cnt_rtl_1|dffs[1], clk_divider:inst3|lpm_counter:cnt_rtl_1|dffs[2], clk_divider:inst3|lpm_counter:cnt_rtl_1|dffs[0], clk_divider:inst3|lpm_counter:cnt_rtl_1|dffs[3], clk_divider:inst2|clk_out ; clk_divider:inst3|lpm_counter:cnt_rtl_1|dffs[1], clk_divider:inst3|lpm_counter:cnt_rtl_1|dffs[3], clk_divider:inst3|clk_out ;
; A ; LC4 ; enable, clk_divider:inst3|lpm_counter:cnt_rtl_1|dffs[1], clk_divider:inst3|lpm_counter:cnt_rtl_1|dffs[0], clk_divider:inst3|lpm_counter:cnt_rtl_1|dffs[2], clk_divider:inst2|clk_out ; clk_divider:inst3|lpm_counter:cnt_rtl_1|dffs[1], clk_divider:inst3|lpm_counter:cnt_rtl_1|dffs[3], clk_divider:inst3|lpm_counter:cnt_rtl_1|dffs[2], clk_divider:inst3|clk_out ;
; E ; LC65 ; enable, clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[1], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[0], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[2], clk_divider:inst|clk_out ; clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[2], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[3], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[5], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[4], clk_divider:inst1|clk_out ;
; E ; LC70 ; enable, clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[1], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[2], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[0], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[3], clk_divider:inst|clk_out ; clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[3], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[5], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[4], clk_divider:inst1|clk_out ;
; E ; LC80 ; clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[4], enable, clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[1], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[2], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[3], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[0], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[5], clk_divider:inst|clk_out ; clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[5], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[4], clk_divider:inst1|clk_out ;
; E ; LC79 ; clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[5], enable, clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[1], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[2], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[3], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[0], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[4], clk_divider:inst|clk_out ; clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[5], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[4], clk_divider:inst1|clk_out ;
; E ; LC78 ; enable, clk_divider:inst1|clk_out, clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[4], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[3], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[5], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[2], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[1], clk_divider:inst1|lpm_counter:cnt_rtl_3|dffs[0], clk_divider:inst|clk_out ; clk_divider:inst1|clk_out, clk_divider:inst2|lpm_counter:cnt_rtl_0|dffs[0], clk_divider:inst2|lpm_counter:cnt_rtl_0|dffs[1], clk_divider:inst2|lpm_counter:cnt_rtl_0|dffs[3], clk_divider:inst2|lpm_counter:cnt_rtl_0|dffs[2], clk_divider:inst2|clk_out ;
; E ; LC76 ; clk_divider:inst2|lpm_counter:cnt_rtl_0|dffs[0], enable, clk_divider:inst1|clk_out ; clk_divider:inst2|lpm_counter:cnt_rtl_0|dffs[0], clk_divider:inst2|lpm_counter:cnt_rtl_0|dffs[1], clk_divider:inst2|lpm_counter:cnt_rtl_0|dffs[3], clk_divider:inst2|lpm_counter:cnt_rtl_0|dffs[2], clk_divider:inst2|clk_out ;
; E ; LC75 ; clk_divider:inst2|lpm_counter:cnt_rtl_0|dffs[2], enable, clk_divider:inst2|lpm_counter:cnt_rtl_0|dffs[1], clk_divider:inst2|lpm_counter:cnt_rtl_0|dffs[0], clk_divider:inst2|lpm_counter:cnt_rtl_0|dffs[3], clk_divider:inst1|clk_out ; clk_divider:inst2|lpm_counter:cnt_rtl_0|dffs[1], clk_divider:inst2|lpm_counter:cnt_rtl_0|dffs[3], clk_divider:inst2|lpm_counter:cnt_rtl_0|dffs[2], clk_divider:inst2|clk_out ;
; E ; LC74 ; enable, clk_divider:inst2|lpm_counter:cnt_rtl_0|dffs[1], clk_divider:inst2|lpm_counter:cnt_rtl_0|dffs[2], clk_divider:inst2|lpm_counter:cnt_rtl_0|dffs[0], clk_divider:inst2|lpm_counter:cnt_rtl_0|dffs[3], clk_divider:inst1|clk_out ; clk_divider:inst2|lpm_counter:cnt_rtl_0|dffs[1], clk_divider:inst2|lpm_counter:cnt_rtl_0|dffs[3], clk_divider:inst2|clk_out ;
; E ; LC66 ; enable, clk_divider:inst2|lpm_counter:cnt_rtl_0|dffs[1], clk_divider:inst2|lpm_counter:cnt_rtl_0|dffs[0], clk_divider:inst2|lpm_counter:cnt_rtl_0|dffs[2], clk_divider:inst1|clk_out ; clk_divider:inst2|lpm_counter:cnt_rtl_0|dffs[1], clk_divider:inst2|lpm_counter:cnt_rtl_0|dffs[3], clk_divider:inst2|lpm_counter:cnt_rtl_0|dffs[2], clk_divider:inst2|clk_out ;
; E ; LC77 ; clk_divider:inst2|clk_out, enable, clk_divider:inst2|lpm_counter:cnt_rtl_0|dffs[2], clk_divider:inst2|lpm_counter:cnt_rtl_0|dffs[0], clk_divider:inst2|lpm_counter:cnt_rtl_0|dffs[3], clk_divider:inst2|lpm_counter:cnt_rtl_0|dffs[1], clk_divider:inst1|clk_out ; clk_divider:inst2|clk_out, 480HZ, clk_divider:inst3|lpm_counter:cnt_rtl_1|dffs[0], clk_divider:inst3|lpm_counter:cnt_rtl_1|dffs[1], clk_divider:inst3|lpm_counter:cnt_rtl_1|dffs[3], clk_divider:inst3|lpm_counter:cnt_rtl_1|dffs[2], clk_divider:inst3|clk_out ;
; E ; LC73 ; enable, clk_divider:inst3|clk_out, clk_divider:inst3|lpm_counter:cnt_rtl_1|dffs[2], clk_divider:inst3|lpm_counter:cnt_rtl_1|dffs[0], clk_divider:inst3|lpm_counter:cnt_rtl_1|dffs[3], clk_divider:inst3|lpm_counter:cnt_rtl_1|dffs[1], clk_divider:inst2|clk_out ; clk_divider:inst3|clk_out, 48HZ, clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[0], clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[1], clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[3], clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[2], clk_divider:inst4|clk_out ;
; E ; LC67 ; enable, clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[0], clk_divider:inst3|clk_out ; clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[0], clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[1], clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[3], clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[2], clk_divider:inst4|clk_out ;
; E ; LC68 ; enable, clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[0], clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[1], clk_divider:inst3|clk_out ; clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[1], clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[3], clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[2], clk_divider:inst4|clk_out ;
; E ; LC71 ; clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[2], clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[1], clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[0], clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[3], enable, clk_divider:inst3|clk_out ; clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[3], clk_divider:inst4|clk_out ;
; E ; LC72 ; enable, clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[1], clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[0], clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[2], clk_divider:inst3|clk_out ; clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[3], clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[2], clk_divider:inst4|clk_out ;
; E ; LC69 ; enable, clk_divider:inst4|clk_out, clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[2], clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[3], clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[1], clk_divider:inst4|lpm_counter:cnt_rtl_2|dffs[0], clk_divider:inst3|clk_out ; clk_divider:inst4|clk_out, 6HZ ;
+-----+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+----------------------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+-----------------------------------------+
; Option ; Setting ;
+----------------------------------------------+-----------------------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Reserve all unused pins ; As output driving an unspecified signal ;
; Security bit ; Off ;
; Base pin-out file on sameframe device ; Off ⌨️ 快捷键说明
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