prev_cmp_clk_divider.qmsg

clock_spliter 採用彈性設計 , 可調整週期寬度.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Web Edition " "Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 15 15:04:13 2008 " "Info: Processing started: Fri Feb 15 15:04:13 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clk_divider -c clk_divider " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clk_divider -c clk_divider" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clk_divider.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file clk_divider.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clk_divider_package " "Info: Found design unit 1: clk_divider_package" {  } { { "clk_divider.vhd" "" { Text "D:/splitter/clk_divider.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 clk_divider-Behaviour " "Info: Found design unit 2: clk_divider-Behaviour" {  } { { "clk_divider.vhd" "" { Text "D:/splitter/clk_divider.vhd" 39 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 clk_divider " "Info: Found entity 1: clk_divider" {  } { { "clk_divider.vhd" "" { Text "D:/splitter/clk_divider.vhd" 30 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock_splitter.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file clock_splitter.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 clock_splitter " "Info: Found entity 1: clock_splitter" {  } { { "clock_splitter.bdf" "" { Schematic "D:/splitter/clock_splitter.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "clk_divider " "Info: Elaborating entity \"clk_divider\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt\[0\]~12 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"cnt\[0\]~12\"" {  } { { "clk_divider.vhd" "cnt\[0\]~12" { Text "D:/splitter/clk_divider.vhd" 45 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../altera/71/quartus/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../altera/71/quartus/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_counter.tdf" 248 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:cnt_rtl_0 " "Info: Elaborated megafunction instantiation \"lpm_counter:cnt_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0 0 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "" 0}  } {  } 0 0 "Promoted pin-driven signal(s) to global signal" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "8 " "Info: Implemented 8 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_MCELLS" "5 " "Info: Implemented 5 macrocells" {  } {  } 0 0 "Implemented %1!d! macrocells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "150 " "Info: Allocated 150 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 15 15:04:23 2008 " "Info: Processing ended: Fri Feb 15 15:04:23 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}